Ethernet Problem in LPC1768

[Prakash]

Hello,

During configuration of Ethernet, JTAG is losing communication with the
target.

In LPC17xx manual there is a remark as follow

Remark: when initializing the Ethernet block, it is important to first configure the PHY and insure that reference clocks (ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK signals in MII mode) are present at the external pins and connected to the EMAC module (selecting the appropriate pins using the PINSEL registers) prior to continuing with Ethernet configuration. Otherwise the CPU can become locked and no further functionality will be possible. This will cause JTAG lose communication with the target, if debug mode is being used.

Hopefully I have initialized correctly. Initialization have following
code,

/* Power Up the EMAC controller. */
SC->PCONP |= 0x40000000;

/* Enable P1 Ethernet Pins. */
PINCON->PINSEL2 = 0x50150105;
PINCON->PINSEL3 = (PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;

/* Reset all EMAC internal modules. */
EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_ TX | MAC1_RES_RX |
MAC1_RES_MCS_ RX |
MAC1_SIM_RES | MAC1_SOFT_RES;
EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;

Is there any problem in this configuration?

KS8721 PHY is the device which I am using in my board. And also I have attached schematic. Please let me know if is there any hardware issues?

Thanks in advance

-Prakash
9886545216

[mark]

Hi Prakash

The code that you show is for the configuration of the Ethernet pins and enabling the EMAC. The warning in the data sheet concerns the PHY and you need to ensure that the PHY's straps are correct when it leaves reset so that it is supplying the correct clocks to the Ethernet controller.

Regards

Mark

[737_pilot]

hi.
i have a lots of advice for this. same uController with KSZ8041RLNI.
i think your problem is related to Phy!. not MAC.
be sure;
* The returned Reference Clock is ok?! this is a reference for MAC module.
* MCFG is the most important settings for LPCs MAC Module. The communication port running <2,5Mhz for many Phy. so you should check your AHB CLock Rate and Ratio.! (i use /44 ratio @100Mhz Cclk)
* PHY Addr is important for reading and writing operation. it can be very dangerous.
* VDDPLL's voltage is ok?
* and if you cannot debug this. you trash your Callback functions. and you should use, direct LPC definitions for configuration.