STM32L031 Clock Tree

This blog entry discusses the clock tree as found in the STM32L031. The clock tree is one of the first things that one is involved with in such new developments. It is assumed that the tree itself is typical for such parts and so that the discussion is in fact of a more general nature than the part actually used as test vehicle.

Clocking in processors has developed a long way from a simple crystal oscillator used to drive most things at a single clock speed. There can be many sources and many choices and the subject has become one that can freighten even experienced developers. So much so that some may start by using some form of clock configuration tool supplied by the chip manufacturer. However the actual code involved is typically only a handful of lines and so basing project tool choice on something with a clock configuration tool just to save these few lines in developments that may run to hundreds of thousands of such lines seems to make much less sense than actually understanding the tree itself. And this is why this dicussion has been written...

Note that there is a (typical) clock module configuration as found in the Kinetis parts at Multipurpose Clock Generator.

We'll start with the clock tree diagram as found in the device's users manual and then elaborate on various details in order to get to know how understand what is going on and how to control it:

Clocking State out of Reset

When the processor starts it has a default clocking configuration which allows it to start running code even without any external clock sources. Specifically it starts with a clock generated by the MSI (Multi-Speed Internal) RC oscillator. In fact this has a number of settings as follows, whereby the accuracy of the frequencies is around +/- 0.5% at normal temperature but can drift by a further +/-3% over the normal temperature range [0..85°C]:

• 65.536kHz
• 131.072kHz
• 262.144kHz
• 524.288kHz
• 1.048MHz
• 2.097MHz - the default frequency
• 4.194MHz

The following diagram shows how the MSI supplies basic clocking to the processor out of reset, whereby some of the control registers and relevant fields are also shown for clarity as to what is controlling this default configuration. It becomes immediately clear that the processor core is running at 2.097MHz, as are the various buses (AHB from HCLK, APB1 and APB2). Peripherals could already be clocked from these sources and the system clock speed verified directly by routing it to the MCO output pin. The speed could also be indirectly verified by using the Cortex SYSTICK to generate interrupts based on its use of HCLK too. Basically, the default state would be suitable for a simple operating program without further adjustments at all!

The µTasker project target configuration #define USE_MSI_CLOCK with #define MSI_CLOCK 2097000 and #define HCLK_DIVIDE 1 can be used to check this.
#define MCO_CONNECTED_TO_MSI additionally connects the frequency to the MCO output pin.
To optionally divide the clock output on the MCO pin, a define #define MCO_DIVIDE 16 can be used, where the value can be 1, 2, 4, 8 or 16.
In order to use other frequencies rather than the MSI's default of approximately 2.097MHz the MSI_CLOCK define value can be set to any of its other possible frequencies.

Standby Mode and Exit from Stand-by

The MSI frequency is controlled by RCC_CR:MSIRANGE[3:0] when the processor is operating in its normal mode (controlled by RCC_CR:MSIRGSEL). When in standby mode the MSI frequency is controlled instead by RCC_CSR:MSIRANGE[3:0], whereby the only frequencies possible in this mode are 1, 2, 4, or 8MHz (the default is 4MHz). After the processor exits from standby mode it is still controlled by the RCC_CSR register value until switched by the application back to RCC_CR control via the RCC_CR:MSIRGSEL bit, which was cleared by hardware when entering the standby mode.

Blog in progress

Updates to follow...