NEW Kirin3 Coldfire V2 family launched today

[neil]

Hi mark,
  I managed to get 60 of the 52259 ordered, and should have them in 2 weeks, and also got the KSZ8041NL too.

Looking at the schematic, it seems that the KZ8041NL uses 2 of the 4 interupts, which only leaves me with 2. In previous processors where I have restricted IRQ lines, I simply use the Input capture interupts. I simply create an interupt on a High to Low transaction. As there are 4 Input capture can I simply set the GPTIMER_SETUP.usCaptureCount =1 so the interupt routine will be processed on each High to Low of the pin? If not what is the best method?

Regards
Neil

[mark]

Hi Neil

In fact the demo board uses up to 3 of the 4 edge port interrupts - the remaining one is has NMI status so needs to be used a bit carefully (can't be masked).

However these line are not absolutely needed. 2 are for communication with the PHY and one for the PHY's interrupt.
The IRQ line is only required if you want an interrupt on things like link state change (otherwise it can be polled).
The communication lines are only needed to set up the IRQ and determine status. If the hardware wired setting is acceptable (eg. always auto-neg.) these can also be left unused (although you won't be able to check to see whether the PHY is responding).

Of course other inputs can be used a timers - like the counter input. also ADC interrupts can be used as level change interrupts be setting triggers to logic levels (this makes 8 additional inputs possible).

Regards

Mark

[neil]

Hi Mark,
  I only need 8 pulse interupts, with fastest being 1 second pulse. As I am not using timer interupts, can the GPT timers be setup for input capture, then simply produce an interupt on evry High to Low pulse?

Neil

[mark]

Hi Neil

Yes, with a capture count of 1 they will effectively operate as an edge interrupt. However there are not 8 such timers - there are however 8 ADC inputs.

Regards

Mark

[neil]

Hi mark,
  Thanks, I made a typo mistake, I meant 4 pulse interupts.

Regards
Neil