µTasker Forum

µTasker Forum => NXPTM M522XX, KINETIS and i.MX RT => Topic started by: neil on January 30, 2009, 01:13:23 PM

Title: reset status flag
Post by: neil on January 30, 2009, 01:13:23 PM
Hi,
  When the processor powers up I would like to check the reset status flag to see  the cause. What register do I use for the 52235 and 52259 (I thought it would be RSR, but no luck)?

Neil
Title: Re: reset status flag
Post by: neil on January 30, 2009, 01:26:07 PM
Hi mark,
  I found it, RESET_RSR. I was looking in the app_hw_m5223x.h instead of m5223x.h
Neil
Title: Re: reset status flag
Post by: mark on January 30, 2009, 02:28:50 PM
Hi Neil

Here are the defines for flags in these registers - they are missing in the present header file:

// Reset Control Module
//
#define RESET_RCR           *(volatile unsigned char *)(RESET_CTRL_ADD + 0x00) // {34} Reset Control Register
  #define SOFT_RST          0x80                                         // Software reset command
  #define FRCRSTOUT         0x40                                         // Assert RSTO signal
  #define LVDF              0x10                                         // Low voltage detected
  #define LVDIE             0x08                                         // Low Voltage Detect Interrupt Enable
  #define LVDRE             0x04                                         // Low Voltage Detect Reset Enable
  #define LVDE              0x01                                         // Low voltage detect is enabled
#define RESET_RSR           *(volatile unsigned char *)(RESET_CTRL_ADD + 0x01) // {34} Reset Status Register (read-only)
  #ifdef BACKUP_WATCHDOG_TIMER_AVAILABLE
    #define RESET_BWT       0x80                                         // Last reset caused by Background Watchdog Timer
  #endif
  #define RESET_LVD         0x40                                         // Last reset caused by Low Voltage Detect
  #define RESET_SOFT        0x20                                         // Last reset caused by Software
  #ifdef BACKUP_WATCHDOG_TIMER_AVAILABLE
    #define RESET_WDR       0x80                                         // Last reset caused by Background Watchdog Timer timeout
  #endif
  #define RESET_POR         0x08                                         // Last reset caused by Power-on
  #define RESET_EXT         0x04                                         // Last reset caused by External reset
  #define RESET_LOC         0x02                                         // Last reset caused by Loss Of Clock
  #define RESET_LOL         0x01                                         // Last reset caused by Loss Of Lock

Regards

Mark
Title: Re: reset status flag
Post by: neil on January 30, 2009, 02:32:33 PM
Hi Mark,
  What exactly is RESET_SOFT? My code is causing this after about 30 minutes running, and currently looking at the cause, but not exactly sure what this is.

Neil
Title: Re: reset status flag
Post by: mark on January 30, 2009, 03:27:15 PM
Hi Neil

This means that the SW commanded a reset.
This happens in 2 circumstance:
- extern void fnResetBoard(void) is called intentionally
- _sw_wdog_timeout() is caused by the Core Watchdog timing out (possibly due to SW getting stuck in a loop or else as consequence of an access error).

I would do the following:
1. Disable watchdog operation - see http://www.utasker.com/docs/M5223X/uTaskerV1.3-Tutorial-M5223X_003.PDF (page 14/34)
2. Run the project with BDM attached with breakpoint in fnResetBoard
3. When the board stops working (it will not reset due to having no active watchdog) pause the debugger and see where it is (if it hasn't hit the breakpoint).

Regards

Mark

Title: Re: reset status flag
Post by: mark on January 30, 2009, 11:34:51 PM
Hi Neil

I have added the last reset cause to the administration side of the web server ready for the next SP.

This is the first time that I have really looked in any detail about the status information so I may need a bit of practice before all reset possibilities are display correctly. What is however apparent is that when using the Background Watchdog Timer a watchdog reset cause can be easily determined. In devices without the BWT the core watchdog doesn't actually generate a reset itself but instead the software is commanding it. This means that a watchdog derived reset doesn't seem to be visible from the reset status register since it looks the same as a software reset.

Here is the present logic which is serving as a starting point:

    if (RESET_RSR == (RESET_POR | RESET_LVD)) {                          // power-on reset
    }
    else if (RESET_RSR & RESET_LVD) {                                    // under voltage
    }
    #ifdef BACKUP_WATCHDOG_TIMER
    else if (RESET_RSR & (RESET_WDR | RESET_BWT)) {                      // background watchdog timer
    }
    #endif
    else if (RESET_RSR & (RESET_LOL & RESET_LOC)) {                      // clock loss
    }
    else if (RESET_RSR & RESET_SOFT) {                                   // commanded reset
    }
    else if (RESET_RSR & RESET_EXT) {                                    // external reset
    }
    else {                                                               // unexpected
    }

Regards

Mark