µTasker Forum

µTasker Forum => NXPTM M522XX, KINETIS and i.MX RT => Topic started by: ehespinosa on February 12, 2010, 02:16:04 PM

Title: CRYSTAL_FREQ
Post by: ehespinosa on February 12, 2010, 02:16:04 PM
I am using a MCF52235 with a CRYSTAL_FREQ 25000000 and I am using Ethernet comunication.

I need increase the clock to 50 or 60 MHZ, can you help me to change the next register configuration

        #define CRYSTAL_FREQ                   25000000                  // 25 MHz oscillator / crystal input
        #define PRE_DIVIDER                    5                         // warning: in first silicon this can not be changed!
        #define OSCCLK                         (CRYSTAL_FREQ / PRE_DIVIDER)
        #define PLL_MUL                        12                        // 60MHz operation

Thanks

Edwiin
Title: Re: CRYSTAL_FREQ
Post by: mark on February 12, 2010, 03:29:20 PM
Hi Edwin

As long as you don't have DISABLE_PLL active the PLL will be set to 60MHz using the settings below.
To run at 50MHz PLL_MUL can be changed to 10

If any settings are invalid, or the frequency generated is out of specification you will get a compiler error, so there is no risk involved when experimenting. Also, when you run the simulator it will show you which PLL speed is actually being used.

Regards

Mark

Title: Re: CRYSTAL_FREQ
Post by: ehespinosa on February 15, 2010, 09:50:07 AM
Hi Mark,

I execute the changes but now I don't have ethernet comunication.

With CRYSTAL_FREQ 60 MHz I defined DISABLE_PLL, and with CRYSTAL_FREQ 50 MHz I defined PLL_MUL 10, But I don't have ETH comunication.

Thanks

Edwin
Title: Re: CRYSTAL_FREQ
Post by: mark on February 15, 2010, 11:28:56 AM
Hi Edwin

You must not disable PLL because this will run at 25MHz. This is probably too low for 100M Ethernet and will only work at 10M.

Regards

Mark

Title: Re: CRYSTAL_FREQ
Post by: ehespinosa on February 15, 2010, 12:18:55 PM
Sorry Mark I could not explain my set register.

Now I working with 50 MHz, this is my register configuration in app_hw_m5223x.h

//#define DISABLE_PLL

#define CRYSTAL_FREQ      50000000
#define PRE_DIVIDER      5
#define OSCCLK         (CRYSTAL_FREQ / PRE_DIVIDER)
#define PLL_MUL         10

I get a compiler error in this part

    #if PLL_OUTPUT_FREQ_INT > MAX_PLL_FREQUENCY
        #error PLL frequency too high!!   
    #endif

Then I no enable last part "//#error PLL frequency too high!!", but I don't have ETH comunication

Regards

Edwin
Title: Re: CRYSTAL_FREQ
Post by: mark on February 15, 2010, 12:55:43 PM
Hi Edwin

The crystal used with the M5223X must be 25MHz.
With CRYSTAL_FREQ 25000000 it should work.

Regards

Mark