µTasker Forum
µTasker Forum => NXPTM M522XX, KINETIS and i.MX RT => Topic started by: Phil on April 30, 2021, 11:19:16 PM
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Mark,
This K64 has a 25MHz crystal connected at XTAL0/EXTAL0. I can't seem to get past the "loop until.." in kinetis_K_CLOCK.h:
while ((MCG_S & MCG_S_IREFST) != 0) { // loop until the FLL source is no longer the internal reference clock
#if defined _WINDOWS
MCG_S &= ~MCG_S_IREFST;
#endif
}
Here is what my app_hw_kinetis.h looks like:
// #define OSC_LOW_GAIN_MODE // oscillator without feedback resistor or load capacitors so use low gain mode
#define CRYSTAL_FREQUENCY 25000000 // 25 MHz crystal
#define EXTERNAL_CLOCK CRYSTAL_FREQUENCY
#define _EXTERNAL_CLOCK EXTERNAL_CLOCK
#define RUN_FROM_EXTERNAL_CLOCK // run directly from external 25MHz clock
#define CLOCK_DIV 10 // input must be divided to 2MHz..4MHz range (/1 to /24)
#define CLOCK_MUL 48 // the PLL multiplication factor to achieve operating frequency of 120MHz (x24 to x55 possible)
#define FLEX_CLOCK_DIVIDE 3 // 120/3 to give 40MHz
#define FLASH_CLOCK_DIVIDE 5 // 120/5 to give 24MHz
// #define USB_CLOCK_GENERATED_INTERNALLY // use USB clock from internal source rather than external pin - 120MHz is suitable from PLL
Am I doing something wrong here? I think it should be working but I don't see anywhere uTasker tells the osc block to use the XTAL0 port then enable the clock.
Thanks.
Phil
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Hi Phil
You need to disable
EXTERNAL_CLOCK
otherwise the code will configure for an "external oscillator" input, which doesn't need the crystal oscillator configured.
Without EXTERNAL_CLOCK it will first configure the oscillator so that the crystal operates and then the clock configuration can complete.
Beware that there is also OSC_LOW_GAIN_MODE (when a crystal oscillator is used) which depends on the crystal oscillator hardware circuit. If is has no loading (no capacitors and no feedback resistor) the low gain mode is suitable, otherwise the low gain mode should be disabled. If this is not set accordingly it is possible that the crystal oscillator can't start up and thus the clock initialisation also can't complete. Once the setting matches the HW there is no further difficulty.
Regards
Mark
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Mark,
Thank you.
Here was my final app_hw_kinetis.h config:
#define OSC_LOW_GAIN_MODE // oscillator without feedback resistor or load capacitors so use low gain mode
#define CRYSTAL_FREQUENCY 25000000 // 25 MHz crystal
#define _EXTERNAL_CLOCK CRYSTAL_FREQUENCY
#define RUN_FROM_EXTERNAL_CLOCK // run directly from external 25MHz clock
#define CLOCK_DIV 10 // input must be divided to 2MHz..4MHz range (/1 to /24)
#define CLOCK_MUL 48 // the PLL multiplication factor to achieve operating frequency of 120MHz (x24 to x55 possible)
#define FLEX_CLOCK_DIVIDE 3 // 120/3 to give 40MHz
#define FLASH_CLOCK_DIVIDE 5 // 120/5 to give 24MHz
#define USB_CLOCK_GENERATED_INTERNALLY // use USB clock from internal source rather than external pin - 120MHz is suitable from PLL
#define USB_CLOCK_SOURCE_MCGPLL1CLK // {29} the clock source for the USB clock is dedicated to the FS USB interface (48MHz)
But, I had to also modify "kinetis_K_CLOCK.h" for the MC6_C1_FRDIV_VALUE for my crystal frequency. It set it to what I thought was closest:
#if !defined RUN_FROM_DEFAULT_CLOCK && !defined EXTERNAL_CLOCK && !defined CLOCK_FROM_RTC_OSCILLATOR // no configuration performed - remain in default clocked mode
#if CRYSTAL_FREQUENCY == 8000000
#define MCG_C1_FRDIV_VALUE MCG_C1_FRDIV_256
#elif CRYSTAL_FREQUENCY == 16000000
#define MCG_C1_FRDIV_VALUE MCG_C1_FRDIV_512
#elif CRYSTAL_FREQUENCY == 24000000
#define MCG_C1_FRDIV_VALUE MCG_C1_FRDIV_1024
#elif CRYSTAL_FREQUENCY >= 10000000 && CRYSTAL_FREQUENCY <= 12000000
#define MCG_C1_FRDIV_VALUE MCG_C1_FRDIV_256
#elif CRYSTAL_FREQUENCY == 4000000
#define MCG_C1_FRDIV_VALUE MCG_C1_FRDIV_128
#elif CRYSTAL_FREQUENCY == 32768
#if !defined FLL_FACTOR
#define MCG_C1_FRDIV_VALUE MCG_C1_FRDIV_RANGE0_1
#endif
#elif CRYSTAL_FREQUENCY == 25000000 // Added by Phil
#define MCG_C1_FRDIV_VALUE MCG_C1_FRDIV_1024
#else
#error crystal speed support needs to be added!
#endif
#endif
Thank you again, Mark.
Phil
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Hi Phil
The FLL divide value is not important when the FLL output is not actually used but the code tries to keep all values in the theoretical spec. limits at all time.
The values for new crystal values were originally added manually as new ones were used but this is an older method now. In the present version this is centralised in kinetis.h with
#if ((_EXTERNAL_CLOCK/32) <= 39062)
#define FLL_INPUT_DIVIDE_VALUE 32
#elif ((_EXTERNAL_CLOCK/64) <= 39062)
#define FLL_INPUT_DIVIDE_VALUE 64
#elif ((_EXTERNAL_CLOCK/128) <= 39062)
#define FLL_INPUT_DIVIDE_VALUE 128
#elif ((_EXTERNAL_CLOCK/256) <= 39062)
#define FLL_INPUT_DIVIDE_VALUE 256
#elif ((_EXTERNAL_CLOCK/512) <= 39062)
#define FLL_INPUT_DIVIDE_VALUE 512
#elif ((_EXTERNAL_CLOCK/1024) <= 39062)
#define FLL_INPUT_DIVIDE_VALUE 1024
#elif ((_EXTERNAL_CLOCK/1280) <= 39062)
#define FLL_INPUT_DIVIDE_VALUE 1280
#elif ((_EXTERNAL_CLOCK/1536) <= 39062)
#define FLL_INPUT_DIVIDE_VALUE 1536
#endif
So that the setting is automatically calculated at compile time and there is no need to maintain a list of supported crystal frequencies.
This is of course a detail since you correctly extended the list as you did it.
Regards
Mark
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Thank you, Mark!
Most appreciated!
Phil