µTasker Forum
µTasker Forum => STTM STM32 and STR91XF => Topic started by: guibiao on July 25, 2008, 04:48:57 PM
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Hi, I try to use the watchdog on the STR912. I init it by
SCU_PRR1 &=~WATCHDOG;
SCU_PRR1 |=WATCHDOG;
WDG_PR = 0xFF;
WDG_VR = 0x027B;
WDG_CR = WATCHDOG_EE;
then, enable it
WDG_CR |= WATCHDOG_WE;
It loads the settings, and starts to count down till reset. When I try to reload the prescale and count by
WDG_KR = 0xA55A;//WDT_FEED1;
WDG_KR = 0x5AA5;//WDT_FEED2;
I could not prevent the wdt from resetting. Please help!
Guibiao
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Hi Guibia
I wonder whether you also need to enable clocks to the watchdog?:
SCU_PCGR1 |= (WATCHDOG); // enable clocks to watchdog
SCU_PRR1 |= (WATCHDOG); // take watchdog module out of reset
Although - if it is counting - it does seem to be working.
I must admit to not having used the watchdog in this chip (in the projects I have performed with it I had no 32kHz [which you seem to be using] and at 96Mhz the maximum timeout was rather short. Due to some encryption routines taking much longer, an external watchdog solution was used instead.
However, when I study your code it does look fine. I do however wonder whether this is compiler optimisation removing the first feed sequence write?
WDG_KR = 0xA55A;//WDT_FEED1; <- may be optimised away by compiler since the second value will result
WDG_KR = 0x5AA5;//WDT_FEED2;
Ensure that WDG_KR is defined as volatile to avoid this possibly happening.
Experiment defining WDG_KR as volatile unsigned long and as volatile unsigned short to ensure that the access length is not critical. I have used devices which have been sensitive to this, although it was not documented anywhere - it then requires a little trial end error until the correct combination is found...
Regards
Mark