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NXPTM LPC2XXX and LPC17XX / Re: LPC2388 & KSZ8721 10Mbit problem
« on: June 02, 2010, 10:49:08 PM »
I'm not sure whether the following has any bearing on what you are investigating, but regarding the Micrel 8721, I've seen that there is a problem with 10MBit when using RMII. If data for transmission is being transferred to the PHY via the RMII interface at just the same time as the first ethernet traffic is arriving at the receive port then the internal FIFO pointers that shuffle the RMII (2-bit wide) data back into MII (4-bit wide) can get corrupted. The upshot is that sometimes the transmitted data on the wire is "out" by two bits. The easiest way to observe this is the 2-bit shorter preamble, but keen observers will see their data followed by two spurious bits on the end of their message on the wire.
Depending on what PHY you then link to determines whether you are even aware of the problem or not. Coupling to another Micrel PHY, or indeed just looping back masks the problem. A short preamble should not be an issue, but an incomplete byte may be. Some PHYs will simply allow each complete byte received to be forwarded, and aren't bothered that two extra bits are sent at the end of the message, while others will detect this and produce an unexpected extra byte on the received message which will then cause each and every message to be discarded downstream.
Once the fault mode has been entered, the PHY FIFOs need to be reset. The best way to avoid the problem is to not send any data on the RMII for transmission until some data has already been received,since it is the start of data RX that triggers a FIFO reset, as best I can recall.
Regards
Depending on what PHY you then link to determines whether you are even aware of the problem or not. Coupling to another Micrel PHY, or indeed just looping back masks the problem. A short preamble should not be an issue, but an incomplete byte may be. Some PHYs will simply allow each complete byte received to be forwarded, and aren't bothered that two extra bits are sent at the end of the message, while others will detect this and produce an unexpected extra byte on the received message which will then cause each and every message to be discarded downstream.
Once the fault mode has been entered, the PHY FIFOs need to be reset. The best way to avoid the problem is to not send any data on the RMII for transmission until some data has already been received,since it is the start of data RX that triggers a FIFO reset, as best I can recall.
Regards