Hi everybody
after 6 hours I found the problem !
Just add MAC_MCFG = (MCFG_RES_MII | MCFG_CLK_SEL); after PCONP |= 0x40000000; in void Init_EMAC(void)
here is complete Init_EMAC():
void Init_EMAC(void)
{
// Keil: function modified to access the EMAC
// Initializes the EMAC ethernet controller
unsigned int regv,tout,id1,id2;
/* Power Up the EMAC controller. */
PCONP |= 0x40000000;
/* reset the MII management interface to disable clock. */
MAC_MCFG = (MCFG_RES_MII | MCFG_CLK_SEL);
/* Enable P1 Ethernet Pins. */
if (MAC_MODULEID == OLD_EMAC_MODULE_ID) {
/* For the first silicon rev.'-' ID P1.6 should be set. */
PINSEL2 = 0x50151105;
}
else {
/* on rev. 'A' and later, P1.6 should NOT be set. */
PINSEL2 = 0x50150105;
}
PINSEL3 = (PINSEL3 & ~0x0000000F) | 0x00000005;
/* Reset all EMAC internal modules. */
MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
MAC1_SIM_RES | MAC1_SOFT_RES;
MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES;
/* A short delay after reset. */
for (tout = 100; tout; tout--);
IODIR1 = 0x1FE00000;
IOCLR1 = 0x1FE00000;
/* Initialize MAC control registers. */
MAC_MAC1 = MAC1_PASS_ALL;
MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
MAC_MAXF = ETH_MAX_FLEN;
MAC_CLRT = CLRT_DEF;
MAC_IPGR = IPGR_DEF;
/* Enable Reduced MII interface. */
MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;
/* Reset Reduced MII Logic. */
MAC_SUPP = SUPP_RES_RMII;
for (tout = 100; tout; tout--);
MAC_SUPP = 0;
/* Put the DP83848C in reset mode */
write_PHY (PHY_REG_BMCR, 0x8000);
/* Wait for hardware reset to end. */
for (tout = 0; tout < 0x100000; tout++) {
regv = read_PHY (PHY_REG_BMCR);
if (!(regv & 0x8000)) {
/* Reset complete */
break;
}
}
/* Check if this is a DP83848C PHY. */
id1 = read_PHY (PHY_REG_IDR1);
id2 = read_PHY (PHY_REG_IDR2);
if (((id1 << 16) | (id2 & 0xFFFF)) == DP83848C_ID) {
/* Configure the PHY device */
/* Use autonegotiation about the link speed. */
write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
/* Wait to complete Auto_Negotiation. */
for (tout = 0; tout < 0x100000; tout++) {
regv = read_PHY (PHY_REG_BMSR);
if (regv & 0x0020) {
/* Autonegotiation Complete. */
break;
}
}
}
/* Check the link status. */
for (tout = 0; tout < 0x10000; tout++) {
regv = read_PHY (PHY_REG_STS);
if (regv & 0x0001) {
/* Link is on. */
break;
}
}
/* Configure Full/Half Duplex mode. */
if (regv & 0x0004) {
/* Full duplex is enabled. */
MAC_MAC2 |= MAC2_FULL_DUP;
MAC_COMMAND |= CR_FULL_DUP;
MAC_IPGT = IPGT_FULL_DUP;
}
else {
/* Half duplex mode. */
MAC_IPGT = IPGT_HALF_DUP;
}
/* Configure 100MBit/10MBit mode. */
if (regv & 0x0002) {
/* 10MBit mode. */
MAC_SUPP = 0;
}
else {
/* 100MBit mode. */
MAC_SUPP = SUPP_SPEED;
}
/* Set the Ethernet MAC Address registers */
MAC_SA0 = (MYMAC_6 <<
| MYMAC_5;
MAC_SA1 = (MYMAC_4 <<
| MYMAC_3;
MAC_SA2 = (MYMAC_2 <<
| MYMAC_1;
/* Initialize Tx and Rx DMA Descriptors */
rx_descr_init ();
tx_descr_init ();
/* Receive Broadcast and Perfect Match Packets */
MAC_RXFILTERCTRL = RFC_BCAST_EN | RFC_PERFECT_EN;
/* Enable EMAC interrupts. */
MAC_INTENABLE = INT_RX_DONE | INT_TX_DONE;
/* Reset all interrupts */
MAC_INTCLEAR = 0xFFFF;
/* Enable receive and transmit mode of MAC Ethernet core */
MAC_COMMAND |= (CR_RX_EN | CR_TX_EN);
MAC_MAC1 |= MAC1_REC_EN;
}
and apply this changes to EMAC.h (line 295)
#define DP83848C_DEF_ADR 0x0000 /* depends on the hardware */
#define DP83848C_ID 0x00221619 /* KS8721HY Identifier */
good luck
regards
Hadi
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