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NXPTM M522XX, KINETIS and i.MX RT / Re: uTasker v2.0.0 doesn't compile on MCUXpresso v11.5.0 (.text LMA overlaps)
« on: March 05, 2026, 03:10:58 AM »
Hi
Make sure that you have switched the repo. to V2.0.0 so that you are using newest source (master source will have linker script files that stopped working with newest GCC versions).
When using MCUXpresso the managed build is not used (where the internal settings are configured) but instead the linker script is entered (see the MCUXpresso guide document or video).
I wouldn't bother changing 8M Flash to 4Meg since it won't change anything. It would just give you an error in case >4 Meg was actually used.
Regards
Mark
P.S: Below is the content of \Applications\uTaskerV1.4\GNU_iMX\iMX_RT_10XX_FlexSPI_NOR.ld as reference
======================================================================
/* iMX_RT_10XX_FlexSPI_NOR.ld - compatible with MCUXpresso > V11.4 */
/* GCC memory file for the iMX RT 10XX - for use with the uTasker project */
/* Use when running from FlexSPI Flash (total up to 512k CPU SRAM) */
_HeapSize = 0x0; /* uTasker project usually does not use library heap */
_StackSize = 0x0; /* uTasker project organises stack at run time */
MEMORY
{
/* Define each memory region */
BOARD_FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 0x800000 /* 8M bytes (alias Flash) */
SRAM_DTC (rwx) : ORIGIN = 0x20000300, LENGTH = 0x80000-0x0300 /* up to 512K bytes (alias RAM) - with vectors at the start */
SRAM_ITC (rwx) : ORIGIN = 0x0, LENGTH = 0x80000 /* up to 512K bytes (alias RAM2) */
SRAM_OC (rwx) : ORIGIN = 0x20200000, LENGTH = 0xc0000 /* 768K bytes (alias RAM3) */
BOARD_SDRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 0x1e00000 /* 30M bytes (alias RAM4) */
NCACHE_REGION (rwx) : ORIGIN = 0x81e00000, LENGTH = 0x200000 /* 2M bytes (alias RAM5) */
}
/* Define a symbol for the top of each memory region */
__base_BOARD_FLASH = 0x60000000 ; /* BOARD_FLASH */
__base_Flash = 0x60000000 ; /* Flash */
__top_BOARD_FLASH = 0x60000000 + 0x800000 ; /* 8M bytes */
__top_Flash = 0x60000000 + 0x800000 ; /* 8M bytes */
__base_SRAM_DTC = 0x20000300 ; /* SRAM_DTC */
__base_RAM = 0x20000000 ; /* RAM */
__top_SRAM_DTC = 0x20000300 + 0x80000 - 0x0300 ; /* up to 512k bytes */
__top_RAM = 0x20000000 + 0x80000 ; /* up to 512k bytes */
__base_SRAM_ITC = 0x0 ; /* SRAM_ITC */
__base_RAM2 = 0x0 ; /* RAM2 */
__top_SRAM_ITC = 0x0 + 0x80000 ; /* up to 512K bytes */
__top_RAM2 = 0x0 + 0x80000 ; /* up to 512K bytes */
__base_SRAM_OC = 0x20200000 ; /* SRAM_OC */
__base_RAM3 = 0x20200000 ; /* RAM3 */
__top_SRAM_OC = 0x20200000 + 0xc0000 ; /* 768K bytes */
__top_RAM3 = 0x20200000 + 0xc0000 ; /* 768K bytes */
__base_BOARD_SDRAM = 0x80000000 ; /* BOARD_SDRAM */
__base_RAM4 = 0x80000000 ; /* RAM4 */
__top_BOARD_SDRAM = 0x80000000 + 0x1e00000 ; /* 30M bytes */
__top_RAM4 = 0x80000000 + 0x1e00000 ; /* 30M bytes */
__base_NCACHE_REGION = 0x81e00000 ; /* NCACHE_REGION */
__base_RAM5 = 0x81e00000 ; /* RAM5 */
__top_NCACHE_REGION = 0x81e00000 + 0x200000 ; /* 2M bytes */
__top_RAM5 = 0x81e00000 + 0x200000 ; /* 2M bytes */
ENTRY(__vector_table)
SECTIONS
{
/* Image Vector Table and Boot Data for booting from external flash */
.boot_hdr : ALIGN(4)
{
FILL(0xff)
__boot_hdr_start__ = ABSOLUTE(.) ;
KEEP(*(.boot_hdr.conf))
. = 0x1000 ;
KEEP(*(.boot_hdr.ivt))
. = 0x1020 ;
KEEP(*(.boot_hdr.boot_data))
. = 0x1030 ;
KEEP(*(.boot_hdr.dcd_data))
. = 0x1fb0 ;
KEEP(*(.boot_hdr.key))
. = 0x1fe0 ;
KEEP(*(.boot_hdr.init))
__boot_hdr_end__ = ABSOLUTE(.) ;
. = 0x2000 ;
} >BOARD_FLASH
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.vectors))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
LONG(LOADADDR(.data_RAM4));
LONG( ADDR(.data_RAM4));
LONG( SIZEOF(.data_RAM4));
LONG(LOADADDR(.data_RAM5));
LONG( ADDR(.data_RAM5));
LONG( SIZEOF(.data_RAM5));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
LONG( ADDR(.bss_RAM4));
LONG( SIZEOF(.bss_RAM4));
LONG( ADDR(.bss_RAM5));
LONG( SIZEOF(.bss_RAM5));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(4);
} > BOARD_FLASH
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > BOARD_FLASH
.ARM.exidx : ALIGN(4)
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > BOARD_FLASH
_etext = .;
/* DATA section for SRAM_ITC */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM2 = .) ;
PROVIDE(__start_data_SRAM_ITC = .) ;
*(.ramfunc.$RAM2)
*(.ramfunc.$SRAM_ITC)
*(.data.$RAM2)
*(.data.$SRAM_ITC)
*(.data.$RAM2.*)
*(.data.$SRAM_ITC.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM2 = .) ;
PROVIDE(__end_data_SRAM_ITC = .) ;
} > SRAM_ITC AT>BOARD_FLASH
/* DATA section for SRAM_OC */
.data_RAM3 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM3 = .) ;
PROVIDE(__start_data_SRAM_OC = .) ;
*(.ramfunc.$RAM3)
*(.ramfunc.$SRAM_OC)
*(.data.$RAM3)
*(.data.$SRAM_OC)
*(.data.$RAM3.*)
*(.data.$SRAM_OC.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM3 = .) ;
PROVIDE(__end_data_SRAM_OC = .) ;
} > SRAM_OC AT>BOARD_FLASH
/* DATA section for BOARD_SDRAM */
.data_RAM4 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM4 = .) ;
PROVIDE(__start_data_BOARD_SDRAM = .) ;
*(.ramfunc.$RAM4)
*(.ramfunc.$BOARD_SDRAM)
*(.data.$RAM4)
*(.data.$BOARD_SDRAM)
*(.data.$RAM4.*)
*(.data.$BOARD_SDRAM.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM4 = .) ;
PROVIDE(__end_data_BOARD_SDRAM = .) ;
} > BOARD_SDRAM AT>BOARD_FLASH
/* DATA section for NCACHE_REGION */
.data_RAM5 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM5 = .) ;
PROVIDE(__start_data_NCACHE_REGION = .) ;
*(.ramfunc.$RAM5)
*(.ramfunc.$NCACHE_REGION)
*(.data.$RAM5)
*(.data.$NCACHE_REGION)
*(.data.$RAM5.*)
*(.data.$NCACHE_REGION.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM5 = .) ;
PROVIDE(__end_data_NCACHE_REGION = .) ;
} > NCACHE_REGION AT>BOARD_FLASH
/* MAIN DATA SECTION */
.uninit_RESERVED (NOLOAD) : ALIGN(4)
{
_start_uninit_RESERVED = .;
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > SRAM_DTC AT> SRAM_DTC
/* Main DATA section (SRAM_DTC) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
PROVIDE(__start_data_RAM = .) ;
PROVIDE(__start_data_SRAM_DTC = .) ;
*(vtable)
*(.ramfunc*)
KEEP(*(CodeQuickAccess))
KEEP(*(DataQuickAccess))
*(RamFunction)
*(NonCacheable.init)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
PROVIDE(__end_data_RAM = .) ;
PROVIDE(__end_data_SRAM_DTC = .) ;
} > SRAM_DTC AT>BOARD_FLASH
/* BSS section for SRAM_ITC */
.bss_RAM2 : ALIGN(4)
{
PROVIDE(__start_bss_RAM2 = .) ;
PROVIDE(__start_bss_SRAM_ITC = .) ;
*(.bss.$RAM2)
*(.bss.$SRAM_ITC)
*(.bss.$RAM2.*)
*(.bss.$SRAM_ITC.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
PROVIDE(__end_bss_SRAM_ITC = .) ;
} > SRAM_ITC AT> SRAM_ITC
/* BSS section for SRAM_OC */
.bss_RAM3 : ALIGN(4)
{
PROVIDE(__start_bss_RAM3 = .) ;
PROVIDE(__start_bss_SRAM_OC = .) ;
*(.bss.$RAM3)
*(.bss.$SRAM_OC)
*(.bss.$RAM3.*)
*(.bss.$SRAM_OC.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM3 = .) ;
PROVIDE(__end_bss_SRAM_OC = .) ;
} > SRAM_OC AT> SRAM_OC
/* BSS section for BOARD_SDRAM */
.bss_RAM4 : ALIGN(4)
{
PROVIDE(__start_bss_RAM4 = .) ;
PROVIDE(__start_bss_BOARD_SDRAM = .) ;
*(.bss.$RAM4)
*(.bss.$BOARD_SDRAM)
*(.bss.$RAM4.*)
*(.bss.$BOARD_SDRAM.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM4 = .) ;
PROVIDE(__end_bss_BOARD_SDRAM = .) ;
} > BOARD_SDRAM AT> BOARD_SDRAM
/* BSS section for NCACHE_REGION */
.bss_RAM5 : ALIGN(4)
{
PROVIDE(__start_bss_RAM5 = .) ;
PROVIDE(__start_bss_NCACHE_REGION = .) ;
*(.bss.$RAM5)
*(.bss.$NCACHE_REGION)
*(.bss.$RAM5.*)
*(.bss.$NCACHE_REGION.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM5 = .) ;
PROVIDE(__end_bss_NCACHE_REGION = .) ;
} > NCACHE_REGION AT> NCACHE_REGION
/* MAIN BSS SECTION */
.bss : ALIGN(4)
{
_bss = .;
PROVIDE(__start_bss_RAM = .) ;
PROVIDE(__start_bss_SRAM_DTC = .) ;
*(NonCacheable)
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(__end_bss_RAM = .) ;
PROVIDE(__end_bss_SRAM_DTC = .) ;
PROVIDE(end = .);
} > SRAM_DTC AT> SRAM_DTC
/* NOINIT section for SRAM_ITC */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM2 = .) ;
PROVIDE(__start_noinit_SRAM_ITC = .) ;
*(.noinit.$RAM2)
*(.noinit.$SRAM_ITC)
*(.noinit.$RAM2.*)
*(.noinit.$SRAM_ITC.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM2 = .) ;
PROVIDE(__end_noinit_SRAM_ITC = .) ;
} > SRAM_ITC AT> SRAM_ITC
/* NOINIT section for SRAM_OC */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM3 = .) ;
PROVIDE(__start_noinit_SRAM_OC = .) ;
*(.noinit.$RAM3)
*(.noinit.$SRAM_OC)
*(.noinit.$RAM3.*)
*(.noinit.$SRAM_OC.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM3 = .) ;
PROVIDE(__end_noinit_SRAM_OC = .) ;
} > SRAM_OC AT> SRAM_OC
/* NOINIT section for BOARD_SDRAM */
.noinit_RAM4 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM4 = .) ;
PROVIDE(__start_noinit_BOARD_SDRAM = .) ;
*(.noinit.$RAM4)
*(.noinit.$BOARD_SDRAM)
*(.noinit.$RAM4.*)
*(.noinit.$BOARD_SDRAM.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM4 = .) ;
PROVIDE(__end_noinit_BOARD_SDRAM = .) ;
} > BOARD_SDRAM AT> BOARD_SDRAM
/* NOINIT section for NCACHE_REGION */
.noinit_RAM5 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM5 = .) ;
PROVIDE(__start_noinit_NCACHE_REGION = .) ;
*(.noinit.$RAM5)
*(.noinit.$NCACHE_REGION)
*(.noinit.$RAM5.*)
*(.noinit.$NCACHE_REGION.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM5 = .) ;
PROVIDE(__end_noinit_NCACHE_REGION = .) ;
} > NCACHE_REGION AT> NCACHE_REGION
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
PROVIDE(__start_noinit_RAM = .) ;
PROVIDE(__start_noinit_SRAM_DTC = .) ;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
PROVIDE(__end_noinit_RAM = .) ;
PROVIDE(__end_noinit_SRAM_DTC = .) ;
} > SRAM_DTC AT> SRAM_DTC
/* Reserve and place Heap within memory map */
.heap (NOLOAD) : ALIGN(4)
{
_pvHeapStart = .;
. += _HeapSize;
. = ALIGN(4);
_pvHeapLimit = .;
} > SRAM_DTC
/* Reserve space in memory for Stack */
.heap2stackfill (NOLOAD) :
{
. += _StackSize;
} > SRAM_DTC
/* Locate actual Stack in memory map */
.stack ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - _StackSize - 0 (NOLOAD) : ALIGN(4)
{
_vStackBase = .;
. = ALIGN(4);
_vStackTop = . + _StackSize;
} > SRAM_DTC
/* Provide basic symbols giving location and size of main text
* block, including initial values of RW data sections. Note that
* these will need extending to give a complete picture with
* complex images (e.g multiple Flash banks).
*/
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
/* For compatibility with uTasker names */
/* */
__data_start__ = _start_uninit_RESERVED;
__data_end__ = __data_start__ + SIZEOF(.data);
__data_load_start__ = LOADADDR (.data);
__bss_start__ = __start_bss_RAM;
__bss_end__ = __start_bss_RAM + SIZEOF(.bss);
__heap_end__ = _pvHeapLimit;
}
Make sure that you have switched the repo. to V2.0.0 so that you are using newest source (master source will have linker script files that stopped working with newest GCC versions).
When using MCUXpresso the managed build is not used (where the internal settings are configured) but instead the linker script is entered (see the MCUXpresso guide document or video).
I wouldn't bother changing 8M Flash to 4Meg since it won't change anything. It would just give you an error in case >4 Meg was actually used.
Regards
Mark
P.S: Below is the content of \Applications\uTaskerV1.4\GNU_iMX\iMX_RT_10XX_FlexSPI_NOR.ld as reference
======================================================================
/* iMX_RT_10XX_FlexSPI_NOR.ld - compatible with MCUXpresso > V11.4 */
/* GCC memory file for the iMX RT 10XX - for use with the uTasker project */
/* Use when running from FlexSPI Flash (total up to 512k CPU SRAM) */
_HeapSize = 0x0; /* uTasker project usually does not use library heap */
_StackSize = 0x0; /* uTasker project organises stack at run time */
MEMORY
{
/* Define each memory region */
BOARD_FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 0x800000 /* 8M bytes (alias Flash) */
SRAM_DTC (rwx) : ORIGIN = 0x20000300, LENGTH = 0x80000-0x0300 /* up to 512K bytes (alias RAM) - with vectors at the start */
SRAM_ITC (rwx) : ORIGIN = 0x0, LENGTH = 0x80000 /* up to 512K bytes (alias RAM2) */
SRAM_OC (rwx) : ORIGIN = 0x20200000, LENGTH = 0xc0000 /* 768K bytes (alias RAM3) */
BOARD_SDRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 0x1e00000 /* 30M bytes (alias RAM4) */
NCACHE_REGION (rwx) : ORIGIN = 0x81e00000, LENGTH = 0x200000 /* 2M bytes (alias RAM5) */
}
/* Define a symbol for the top of each memory region */
__base_BOARD_FLASH = 0x60000000 ; /* BOARD_FLASH */
__base_Flash = 0x60000000 ; /* Flash */
__top_BOARD_FLASH = 0x60000000 + 0x800000 ; /* 8M bytes */
__top_Flash = 0x60000000 + 0x800000 ; /* 8M bytes */
__base_SRAM_DTC = 0x20000300 ; /* SRAM_DTC */
__base_RAM = 0x20000000 ; /* RAM */
__top_SRAM_DTC = 0x20000300 + 0x80000 - 0x0300 ; /* up to 512k bytes */
__top_RAM = 0x20000000 + 0x80000 ; /* up to 512k bytes */
__base_SRAM_ITC = 0x0 ; /* SRAM_ITC */
__base_RAM2 = 0x0 ; /* RAM2 */
__top_SRAM_ITC = 0x0 + 0x80000 ; /* up to 512K bytes */
__top_RAM2 = 0x0 + 0x80000 ; /* up to 512K bytes */
__base_SRAM_OC = 0x20200000 ; /* SRAM_OC */
__base_RAM3 = 0x20200000 ; /* RAM3 */
__top_SRAM_OC = 0x20200000 + 0xc0000 ; /* 768K bytes */
__top_RAM3 = 0x20200000 + 0xc0000 ; /* 768K bytes */
__base_BOARD_SDRAM = 0x80000000 ; /* BOARD_SDRAM */
__base_RAM4 = 0x80000000 ; /* RAM4 */
__top_BOARD_SDRAM = 0x80000000 + 0x1e00000 ; /* 30M bytes */
__top_RAM4 = 0x80000000 + 0x1e00000 ; /* 30M bytes */
__base_NCACHE_REGION = 0x81e00000 ; /* NCACHE_REGION */
__base_RAM5 = 0x81e00000 ; /* RAM5 */
__top_NCACHE_REGION = 0x81e00000 + 0x200000 ; /* 2M bytes */
__top_RAM5 = 0x81e00000 + 0x200000 ; /* 2M bytes */
ENTRY(__vector_table)
SECTIONS
{
/* Image Vector Table and Boot Data for booting from external flash */
.boot_hdr : ALIGN(4)
{
FILL(0xff)
__boot_hdr_start__ = ABSOLUTE(.) ;
KEEP(*(.boot_hdr.conf))
. = 0x1000 ;
KEEP(*(.boot_hdr.ivt))
. = 0x1020 ;
KEEP(*(.boot_hdr.boot_data))
. = 0x1030 ;
KEEP(*(.boot_hdr.dcd_data))
. = 0x1fb0 ;
KEEP(*(.boot_hdr.key))
. = 0x1fe0 ;
KEEP(*(.boot_hdr.init))
__boot_hdr_end__ = ABSOLUTE(.) ;
. = 0x2000 ;
} >BOARD_FLASH
/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.vectors))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
LONG(LOADADDR(.data_RAM4));
LONG( ADDR(.data_RAM4));
LONG( SIZEOF(.data_RAM4));
LONG(LOADADDR(.data_RAM5));
LONG( ADDR(.data_RAM5));
LONG( SIZEOF(.data_RAM5));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
LONG( ADDR(.bss_RAM4));
LONG( SIZEOF(.bss_RAM4));
LONG( ADDR(.bss_RAM5));
LONG( SIZEOF(.bss_RAM5));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(4);
} > BOARD_FLASH
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > BOARD_FLASH
.ARM.exidx : ALIGN(4)
{
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > BOARD_FLASH
_etext = .;
/* DATA section for SRAM_ITC */
.data_RAM2 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM2 = .) ;
PROVIDE(__start_data_SRAM_ITC = .) ;
*(.ramfunc.$RAM2)
*(.ramfunc.$SRAM_ITC)
*(.data.$RAM2)
*(.data.$SRAM_ITC)
*(.data.$RAM2.*)
*(.data.$SRAM_ITC.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM2 = .) ;
PROVIDE(__end_data_SRAM_ITC = .) ;
} > SRAM_ITC AT>BOARD_FLASH
/* DATA section for SRAM_OC */
.data_RAM3 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM3 = .) ;
PROVIDE(__start_data_SRAM_OC = .) ;
*(.ramfunc.$RAM3)
*(.ramfunc.$SRAM_OC)
*(.data.$RAM3)
*(.data.$SRAM_OC)
*(.data.$RAM3.*)
*(.data.$SRAM_OC.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM3 = .) ;
PROVIDE(__end_data_SRAM_OC = .) ;
} > SRAM_OC AT>BOARD_FLASH
/* DATA section for BOARD_SDRAM */
.data_RAM4 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM4 = .) ;
PROVIDE(__start_data_BOARD_SDRAM = .) ;
*(.ramfunc.$RAM4)
*(.ramfunc.$BOARD_SDRAM)
*(.data.$RAM4)
*(.data.$BOARD_SDRAM)
*(.data.$RAM4.*)
*(.data.$BOARD_SDRAM.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM4 = .) ;
PROVIDE(__end_data_BOARD_SDRAM = .) ;
} > BOARD_SDRAM AT>BOARD_FLASH
/* DATA section for NCACHE_REGION */
.data_RAM5 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM5 = .) ;
PROVIDE(__start_data_NCACHE_REGION = .) ;
*(.ramfunc.$RAM5)
*(.ramfunc.$NCACHE_REGION)
*(.data.$RAM5)
*(.data.$NCACHE_REGION)
*(.data.$RAM5.*)
*(.data.$NCACHE_REGION.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM5 = .) ;
PROVIDE(__end_data_NCACHE_REGION = .) ;
} > NCACHE_REGION AT>BOARD_FLASH
/* MAIN DATA SECTION */
.uninit_RESERVED (NOLOAD) : ALIGN(4)
{
_start_uninit_RESERVED = .;
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > SRAM_DTC AT> SRAM_DTC
/* Main DATA section (SRAM_DTC) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
PROVIDE(__start_data_RAM = .) ;
PROVIDE(__start_data_SRAM_DTC = .) ;
*(vtable)
*(.ramfunc*)
KEEP(*(CodeQuickAccess))
KEEP(*(DataQuickAccess))
*(RamFunction)
*(NonCacheable.init)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
PROVIDE(__end_data_RAM = .) ;
PROVIDE(__end_data_SRAM_DTC = .) ;
} > SRAM_DTC AT>BOARD_FLASH
/* BSS section for SRAM_ITC */
.bss_RAM2 : ALIGN(4)
{
PROVIDE(__start_bss_RAM2 = .) ;
PROVIDE(__start_bss_SRAM_ITC = .) ;
*(.bss.$RAM2)
*(.bss.$SRAM_ITC)
*(.bss.$RAM2.*)
*(.bss.$SRAM_ITC.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
PROVIDE(__end_bss_SRAM_ITC = .) ;
} > SRAM_ITC AT> SRAM_ITC
/* BSS section for SRAM_OC */
.bss_RAM3 : ALIGN(4)
{
PROVIDE(__start_bss_RAM3 = .) ;
PROVIDE(__start_bss_SRAM_OC = .) ;
*(.bss.$RAM3)
*(.bss.$SRAM_OC)
*(.bss.$RAM3.*)
*(.bss.$SRAM_OC.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM3 = .) ;
PROVIDE(__end_bss_SRAM_OC = .) ;
} > SRAM_OC AT> SRAM_OC
/* BSS section for BOARD_SDRAM */
.bss_RAM4 : ALIGN(4)
{
PROVIDE(__start_bss_RAM4 = .) ;
PROVIDE(__start_bss_BOARD_SDRAM = .) ;
*(.bss.$RAM4)
*(.bss.$BOARD_SDRAM)
*(.bss.$RAM4.*)
*(.bss.$BOARD_SDRAM.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM4 = .) ;
PROVIDE(__end_bss_BOARD_SDRAM = .) ;
} > BOARD_SDRAM AT> BOARD_SDRAM
/* BSS section for NCACHE_REGION */
.bss_RAM5 : ALIGN(4)
{
PROVIDE(__start_bss_RAM5 = .) ;
PROVIDE(__start_bss_NCACHE_REGION = .) ;
*(.bss.$RAM5)
*(.bss.$NCACHE_REGION)
*(.bss.$RAM5.*)
*(.bss.$NCACHE_REGION.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM5 = .) ;
PROVIDE(__end_bss_NCACHE_REGION = .) ;
} > NCACHE_REGION AT> NCACHE_REGION
/* MAIN BSS SECTION */
.bss : ALIGN(4)
{
_bss = .;
PROVIDE(__start_bss_RAM = .) ;
PROVIDE(__start_bss_SRAM_DTC = .) ;
*(NonCacheable)
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(__end_bss_RAM = .) ;
PROVIDE(__end_bss_SRAM_DTC = .) ;
PROVIDE(end = .);
} > SRAM_DTC AT> SRAM_DTC
/* NOINIT section for SRAM_ITC */
.noinit_RAM2 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM2 = .) ;
PROVIDE(__start_noinit_SRAM_ITC = .) ;
*(.noinit.$RAM2)
*(.noinit.$SRAM_ITC)
*(.noinit.$RAM2.*)
*(.noinit.$SRAM_ITC.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM2 = .) ;
PROVIDE(__end_noinit_SRAM_ITC = .) ;
} > SRAM_ITC AT> SRAM_ITC
/* NOINIT section for SRAM_OC */
.noinit_RAM3 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM3 = .) ;
PROVIDE(__start_noinit_SRAM_OC = .) ;
*(.noinit.$RAM3)
*(.noinit.$SRAM_OC)
*(.noinit.$RAM3.*)
*(.noinit.$SRAM_OC.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM3 = .) ;
PROVIDE(__end_noinit_SRAM_OC = .) ;
} > SRAM_OC AT> SRAM_OC
/* NOINIT section for BOARD_SDRAM */
.noinit_RAM4 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM4 = .) ;
PROVIDE(__start_noinit_BOARD_SDRAM = .) ;
*(.noinit.$RAM4)
*(.noinit.$BOARD_SDRAM)
*(.noinit.$RAM4.*)
*(.noinit.$BOARD_SDRAM.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM4 = .) ;
PROVIDE(__end_noinit_BOARD_SDRAM = .) ;
} > BOARD_SDRAM AT> BOARD_SDRAM
/* NOINIT section for NCACHE_REGION */
.noinit_RAM5 (NOLOAD) : ALIGN(4)
{
PROVIDE(__start_noinit_RAM5 = .) ;
PROVIDE(__start_noinit_NCACHE_REGION = .) ;
*(.noinit.$RAM5)
*(.noinit.$NCACHE_REGION)
*(.noinit.$RAM5.*)
*(.noinit.$NCACHE_REGION.*)
. = ALIGN(4) ;
PROVIDE(__end_noinit_RAM5 = .) ;
PROVIDE(__end_noinit_NCACHE_REGION = .) ;
} > NCACHE_REGION AT> NCACHE_REGION
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(4)
{
_noinit = .;
PROVIDE(__start_noinit_RAM = .) ;
PROVIDE(__start_noinit_SRAM_DTC = .) ;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
PROVIDE(__end_noinit_RAM = .) ;
PROVIDE(__end_noinit_SRAM_DTC = .) ;
} > SRAM_DTC AT> SRAM_DTC
/* Reserve and place Heap within memory map */
.heap (NOLOAD) : ALIGN(4)
{
_pvHeapStart = .;
. += _HeapSize;
. = ALIGN(4);
_pvHeapLimit = .;
} > SRAM_DTC
/* Reserve space in memory for Stack */
.heap2stackfill (NOLOAD) :
{
. += _StackSize;
} > SRAM_DTC
/* Locate actual Stack in memory map */
.stack ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - _StackSize - 0 (NOLOAD) : ALIGN(4)
{
_vStackBase = .;
. = ALIGN(4);
_vStackTop = . + _StackSize;
} > SRAM_DTC
/* Provide basic symbols giving location and size of main text
* block, including initial values of RW data sections. Note that
* these will need extending to give a complete picture with
* complex images (e.g multiple Flash banks).
*/
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
/* For compatibility with uTasker names */
/* */
__data_start__ = _start_uninit_RESERVED;
__data_end__ = __data_start__ + SIZEOF(.data);
__data_load_start__ = LOADADDR (.data);
__bss_start__ = __start_bss_RAM;
__bss_end__ = __start_bss_RAM + SIZEOF(.bss);
__heap_end__ = _pvHeapLimit;
}