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Messages - jackking

Pages: [1] 2 3
1
NXPTM M522XX, KINETIS and i.MX RT / reinstalling serial loader with fallback loader, how to start fallback loader?
« on: April 07, 2024, 03:42:12 PM »
I am reading the test drive document for the Serial Loader: https://www.utasker.com/docs/iMX/uTaskerLoader_TestDrive.pdf

the doc mentions:
"recovery via serial “Fall-back” loader when a faulty application or a faulty serial loader is installed"

But the doc doesn't describe how this actually happens.   How does uTaskerBoot know to start the fallback loader instead of the serial loader if the serial loader is corrupted?

I see the fallback loader start if the serial loader is missing completely, but how would this work if the serial loader is present, but corrupted or needs to be updated?

thanks




2
NXPTM M522XX, KINETIS and i.MX RT / Re: Jumping to SerialLoader from flashloader (blhost)?
« on: April 07, 2024, 03:37:27 PM »
Thanks for the reply, I am going to continue trying to get my blhost based reset working with my existing flashloader (based on the NXP mcu-boot project).

I will update here if I have any success.


3
NXPTM M522XX, KINETIS and i.MX RT / Jumping to SerialLoader from flashloader (blhost)?
« on: April 03, 2024, 03:15:18 PM »
I am trying to completely automate my dev cycle, using command line sdphost to load the flashloader, then blhost to write the uTasker Serial Loader.  This is instead of using MCU Boot Utility.

I can get the SerialLoader written to flash without issues, but I would like to then cause blhost to jump to execution of the SerialLoader.

I tried following this approach: https://community.nxp.com/t5/MCUXpresso-Secure-Provisioning/BLHost-Execute-application-from-NOR/td-p/1546972

It does jump, but the SerialLoader doesn't seem to actually execute correctly, so I must be missing something.

Has anyone tried this with the uTasker SerialLoader?

Here are my commands to try and execute the jump from blhost:
Code: [Select]
../secure_provisioning/blhost -t 5242000 -u 0x15A2,0x0073 -- read-memory 0x60001000 8
Inject command 'read-memory'
Successful response to command 'read-memory'

d1 00 20 41 00 20 00 60

(1/1)100% Completed!
Successful generic response to command 'read-memory'
Response status = 0 (0x0) Success.
Response word 1 = 8 (0x8)
Read 8 of 8 bytes.

Application address:  0x60002000
../secure_provisioning/blhost -t 5242000 -u 0x15A2,0x0073 -- read-memory 0x60002000 8
Inject command 'read-memory'
Successful response to command 'read-memory'

00 c0 2b 20 61 33 00 60

(1/1)100% Completed!
Successful generic response to command 'read-memory'
Response status = 0 (0x0) Success.
Response word 1 = 8 (0x8)
Read 8 of 8 bytes.

Stack pointer:  0x202bc000
Reset vector:  0x60003361
../secure_provisioning/blhost -u 0x15A2,0x0073 -- execute 0x60003361 0 0x202bc000
Inject command 'execute'
Successful generic response to command 'execute'
Response status = 0 (0x0) Success.


4
NXPTM M522XX, KINETIS and i.MX RT / Re: Set up for ADC on i.MX RT... not getting it.
« on: March 21, 2024, 09:19:42 PM »
ah, thanks!  That is working now.  I may forgo the chaining for this test, I am just trying to understand the ADC setup.

5
NXPTM M522XX, KINETIS and i.MX RT / Set up for ADC on i.MX RT... not getting it.
« on: March 21, 2024, 05:24:10 PM »
I am trying to do some extra credit in my SerialLoader and have a test routine that reads ADC inputs, but I'm not having much luck.

I see various other posts about the ADC, I have checked ADC_Timers.h for example config as well as the pdf on ADC usage, but I still get no reading.

I have two inputs on the i.MX RT (1062), GPIO_AD_B1_04 and GPIO_AD_B1_05. which have the analog voltage coming in.  Using the NXP MCUXpresso SDK, I am able to set up ADC_ETC and the ADC channels 1 and 2 with chaining to successfully read both inputs after a chained conversion is triggered by a PIT.

Using uTasker, I don't really have a clue where to start...

I don't know how to understand the mapping of the actual pins applies to the ADC_SETUP.  I assume that the int_adc_bit should define this using one of the ADC_SE defines in iMX.h:
Code: [Select]
#define ADC_SE0_SINGLE          0
#define ADC_SE1_SINGLE          1
#define ADC_SE2_SINGLE          2
#define ADC_SE3_SINGLE          3
#define ADC_SE4_SINGLE          4
#define ADC_SE5_SINGLE          5
#define ADC_SE6_SINGLE          6
#define ADC_SE7_SINGLE          7
#define ADC_SE8_SINGLE          8
#define ADC_SE9_SINGLE          9
#define ADC_SE10_SINGLE         10
#define ADC_SE11_SINGLE         11
#define ADC_SE12_SINGLE         12
#define ADC_SE13_SINGLE         13
#define ADC_SE14_SINGLE         14
#define ADC_SE15_SINGLE         15
#define ADC_ETC_SINGLE          16
But it also mentions these should map to inputs 0...31 (?). and I see ADC_ETC as well, but I don't see how to set that up.

I also see some of the examples seem to set the int_handler multiple times before setting the actual interrupt, wouldn't this just overwrite the previous value and have no effect?
For example in the ADC pdf it has:
Code: [Select]
ADC_SETUP adc_setup; // interrupt configuration parameters
adc_setup.int_type = ADC_INTERRUPT; // identifier when configuring
adc_setup.pga_gain = PGA_GAIN_OFF; // PGA gain can be specified for certain inputs
adc_setup.int_handler = fnRangeInterrupt; // handling function
adc_setup.int_priority = PRIORITY_ADC; // ADC interrupt priority
adc_setup.int_adc_controller = 1; // ADC controller 1
adc_setup.int_adc_offset = 0; // no offset
adc_setup.int_adc_mode = (ADC_CALIBRATE | ADC_SELECT_INPUTS_A | ADC_CLOCK_BUS_DIV_2 |
ADC_CLOCK_DIVIDE_8 | ADC_SAMPLE_ACTIVATE_LONG | ADC_CONFIGURE_ADC | ADC_REFERENCE_VREF |
ADC_CONFIGURE_CHANNEL | ADC_SINGLE_ENDED | ADC_SINGLE_SHOT_MODE | ADC_12_BIT_MODE |
ADC_SW_TRIGGERED); // calibrate the ADC - single shot with interrupt on completion
adc_setup.int_adc_sample = (ADC_SAMPLE_LONG_PLUS_12 | ADC_SAMPLE_AVERAGING_32);
// additional sampling clocks
adc_setup.int_adc_result = 0; // no result is requested
adc_setup.int_adc_bit = ADC_DM1_SINGLE; // ADC DM1 single-ended
adc_setup.int_adc_bit_b = ADC_DISABLED; // channel B only valid in HW triggered mode
adc_setup.int_adc_int_type = (ADC_LOW_LIMIT_INT);
// interrupt type (trigger only when lower than the defined level)
adc_setup.int_low_level_trigger = (unsigned short)(ADC_VOLT * 1.3);
// the low level trigger threshold represented as input voltage
adc_setup.int_handler = adc_ready_1; // handling function
Which sets the int_handler twice, once to fnRangeInterrupt and then to adc_ready_1 at the end. How is this supposed to work?

Here is the code I have been trying to get working as a test on the iMX:

Code: [Select]
ADC_RESULTS  samples;

void fnADCresult()
{
// get the sample
fnDebugMsg("ADC SAMPLE: ");
fnDebugHex((unsigned short) samples.sADC_value[0], (sizeof(unsigned short) | WITH_LEADIN | WITH_CR_LF));

        // set up for the next sample (after we get this working once)
}

void fnInitializePots(void)
{
fnDebugMsg("INIT ADC\r\n");

    // set the ADC input pins?
    _CONFIG_PORT_INPUT(6, PIN_GPIO_AD_B1_04_GPIO6_IO20, (0));
    _CONFIG_PORT_INPUT(6, PIN_GPIO_AD_B1_05_GPIO6_IO21, (0));

    // now we need to set up the ADC to read the pot values
    ADC_SETUP adc_setup; // interrupt configuration parameters
    adc_setup.int_type = ADC_INTERRUPT; // identifier when configuring
    adc_setup.pga_gain = PGA_GAIN_OFF; // PGA gain can be specified for certain inputs
    adc_setup.int_priority = PRIORITY_ADC; // ADC interrupt priority
    adc_setup.int_adc_controller = iMX_ADC_1;                            // first i.MX RT ADC
    adc_setup.int_handler = 0; // handling function, removed for now
    adc_setup.int_adc_bit = ADC_SE10_SINGLE;                              // which pin is this?
    adc_setup.int_adc_offset = 0; // no offset
    adc_setup.int_adc_mode = (ADC_CALIBRATE | ADC_SELECT_INPUTS_A | ADC_CLOCK_BUS_DIV_2 | ADC_CLOCK_DIVIDE_8 | ADC_SAMPLE_ACTIVATE_LONG | ADC_CONFIGURE_ADC | ADC_REFERENCE_VREF | ADC_CONFIGURE_CHANNEL | ADC_SINGLE_ENDED_INPUT | ADC_SINGLE_SHOT_MODE | ADC_12_BIT_MODE | ADC_SW_TRIGGERED); // note that the first configuration should calibrate the ADC - single shot with interrupt on completion {12}
    adc_setup.int_adc_sample = (ADC_SAMPLE_LONG_PLUS_12 | ADC_SAMPLE_AVERAGING_32);
    // additional sampling clocks
    adc_setup.int_adc_result = &samples;
    adc_setup.int_adc_bit_b = ADC_DISABLED; // channel B only valid in HW triggered mode
    adc_setup.int_adc_int_type = (ADC_END_OF_SCAN_INT);


    fnConfigureInterrupt((void *)&adc_setup);                            // configure and start next sequence
    fnADCresult();

}
This results in a value of 0x0000. from the result (which isn't correct).

After/if I get this working, I definitely wouldn't know how to get chaining to work for using both inputs at the same time!

Thanks




6
µTasker general / Re: Method for Serial Loader to track application version?
« on: March 19, 2024, 02:44:39 PM »
I added a version to the boot_header file and then modified the loader to handle it for checking the version number and file validity (since it was looking for 0xff in those bytes).  Now I can quickly check if a new application is a newer version vs. doing a byte for byte compare every time.

Code: [Select]
// We add 760 bytes of padding between the header and the start of code in order to
// align the code on a 1k byte boundary (ensures on-the-fly decryption compatibility,
// library compatibility and also allows interrupt vectors to remain in code)

02f8                   // first two bytes specify the length
0f0000        // specify DTC/ITC and OCR
00010000               // version 00 01 00 00   = version 01.00
ffffffffffffff
ffffffffffffffff

ffffffffffffffff
ffffffffffffffff
ffffffffffffffff
ffffffffffffffff

ffffffffffffffff
ffffffffffffffff
ffffffffffffffff
ffffffffffffffff

7
NXPTM M522XX, KINETIS and i.MX RT / Re: Caching of (XiP) Flash?
« on: March 13, 2024, 05:47:45 PM »
Awesome, that's seems to have worked for me as well.

Thanks!

8
NXPTM M522XX, KINETIS and i.MX RT / Caching of (XiP) Flash?
« on: March 13, 2024, 01:09:16 AM »
I am having a situation where immediately after clearing flash in the SerialLoader, reading back from flash returns the old value before the erase.  Is there a cache for the external Flash that needs to be flushed?

I tried fnCommandCache(INSTRUCTION_CACHE_INVALIDATE | DATA_CACHE_INVALIDATE);  But that seems to only be for the TCM memories.

thanks

9
NXPTM M522XX, KINETIS and i.MX RT / Re: un-enumerate USB Device loader?
« on: March 09, 2024, 11:17:07 PM »
I just tried this approach and it works well.  Thanks!


10
NXPTM M522XX, KINETIS and i.MX RT / Re: un-enumerate USB Device loader?
« on: February 28, 2024, 08:10:29 PM »
Thanks, I will give that a shot.  I changed the loader to not automatically reset when the file is copied and verified via USB-MSD-DEVICE. 

I just want the USB to un-enumerate after the file copy so the drive disappears.  Then the user can either "try again" and reenumerate, or the update continues and then the user is prompted to reset (boot the application) when they choose.

11
µTasker general / Re: Method for Serial Loader to track application version?
« on: February 28, 2024, 05:37:37 PM »
Mark,

I have customized all loader methods (SD card, USB-MSD host and device and Serial) to store the incoming application into SDRAM first (since the part I am using does have a large SDRAM area).  Then I perform the update of Flash from the SDRAM data.  I can check the application version as part of this process, to perform a fast check before using a longer flash comparison and CRC calculation.  This would be compared to the existing application version in Flash.

I just didn't know if the "standard" uTasker application tools also had some way to add a version number when creating the application file, or whether I should handle this in my own way.

Thanks
JK

12
µTasker general / Method for Serial Loader to track application version?
« on: February 27, 2024, 11:58:22 PM »
I am looking at using a version number on my application to see if the Serial Loader should perform an update, instead of doing a byte for byte check of flash to compare the current application with the incoming file to see if they are the same.

Is there already this concept built into the Serial Loader?   

Otherwise, I will look at modifying the application header to include a version in the update file and check this against the application in flash with a modified Serial Loader.

thanks
JK

13
NXPTM M522XX, KINETIS and i.MX RT / Re: Serial Loader: Placing vars into SDRAM?
« on: February 27, 2024, 04:52:51 PM »
I did a little more investigating on this, and it seems there are still some problems with the modified linker files in later MCUXpresso versions. 

My uploaded application could not run after booting from the Serial Loader. 

Moving the same application over to MCUXpresso 11.4 and using the old linker scripts, the same application would run.


14
NXPTM M522XX, KINETIS and i.MX RT / un-enumerate USB Device loader?
« on: February 27, 2024, 04:49:01 PM »
I would like to un-enumerate (disconnect) the uTasker USB device after a successful upload of a firmware file.  Is there a way to create a function opposite of the
Code: [Select]
fnConfigureUSB(void) function to call before suspending the task?

thanks
JK

15
NXPTM M522XX, KINETIS and i.MX RT / Re: Serial Loader: Placing vars into SDRAM?
« on: February 09, 2024, 02:38:49 PM »
OK, I have created my own SEMC init function (from the code in glcd_tft.h) and that seems to work.  This would seem to indicate that either the DCD data is not correct or not getting applied in the uTaskerBoot code...

Here is the SEMC init code I am using:

Code: [Select]
void fnInitSEMC(void) {

#if (defined MIMXRT1050 || defined iMX_RT1052_EMB_ART || defined iMX_RT1062_EMB_ART || defined MIMXRT1060  || defined MIMXRT1064) // {8}

#if (!defined SDRAM_CONFIGURED_BY_DCD)
// Configure SEMC pins and SDRAM (IS42S16160J-6BLI)
//
_CONFIG_PERIPHERAL(GPIO_EMC_00, SEMC_DATA00,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA00 on GPIO4-00 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_01, SEMC_DATA01,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA01 on GPIO4-01 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_02, SEMC_DATA02,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA02 on GPIO4-02 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_03, SEMC_DATA03,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA03 on GPIO4-03 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_04, SEMC_DATA04,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA04 on GPIO4-04 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_05, SEMC_DATA05,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA05 on GPIO4-05 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_06, SEMC_DATA06,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA06 on GPIO4-06 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_07, SEMC_DATA07,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA07 on GPIO4-07 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_30, SEMC_DATA08,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA08 on GPIO4-30 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_31, SEMC_DATA09,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA09 on GPIO4-31 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_32, SEMC_DATA10,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA10 on GPIO3-18 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_33, SEMC_DATA11,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA11 on GPIO3-19 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_34, SEMC_DATA12,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA12 on GPIO3-20 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_35, SEMC_DATA13,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA13 on GPIO3-21 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_36, SEMC_DATA14,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA14 on GPIO3-22 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_37, SEMC_DATA15,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA15 on GPIO3-23 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_09, SEMC_ADDR00,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR00 on GPIO4-09 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_10, SEMC_ADDR01,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR01 on GPIO4-10 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_11, SEMC_ADDR02,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR02 on GPIO4-11 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_12, SEMC_ADDR03,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR03 on GPIO4-12 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_13, SEMC_ADDR04,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR04 on GPIO4-13 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_14, SEMC_ADDR05,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR05 on GPIO4-14 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_15, SEMC_ADDR06,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR06 on GPIO4-15 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_16, SEMC_ADDR07,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR07 on GPIO4-16 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_17, SEMC_ADDR08,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR08 on GPIO4-17 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_18, SEMC_ADDR09,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR09 on GPIO4-18 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_23, SEMC_ADDR10,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR10 on GPIO4-23 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_19, SEMC_ADDR11,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR11 on GPIO4-19 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_20, SEMC_ADDR12,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR12 on GPIO4-20 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_21, SEMC_BA0,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_BA0 on GPIO4-21 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_22, SEMC_BA1,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_BA1 on GPIO4-22 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_24, SEMC_CAS,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_CAS on GPIO4-24 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_25, SEMC_RAS,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_RAS on GPIO4-25 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_26, SEMC_CLK,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_CLK on GPIO4-26 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_27, SEMC_CKE,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_CKE on GPIO4-27 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_28, SEMC_WE,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_WE on GPIO4-28 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_29, SEMC_CS0,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_CS0 on GPIO4-29 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_08, SEMC_DM00,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DM00 on GPIO4-08 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_38, SEMC_DM01,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DM01 on GPIO3-24 - alt function 0 (direction output)
POWER_UP_ATOMIC(1, SEMC_EXSC_CLOCK);
POWER_UP_ATOMIC(3, SEMC_CLOCKS);
#if defined iMX_RT1062
#if defined APPLICATION_REQUIRES_GPIO_EMC_39
SEMC_MCR = 0; // dummy read strobe loop backed internally - maximum 60MHz operation
#else
SEMC_MCR = (SEMC_MCR_BTO_DEFAULT | SEMC_MCR_DQSMD); // DQS (read strobe) mode (maximum speed possible)
#endif
#else
#if defined APPLICATION_REQUIRES_GPIO_EMC_39
SEMC_MCR = 0; // dummy read strobe loop backed internally - maximum 60MHz operation
#else
SEMC_MCR = (SEMC_MCR_DQSMD); // DQS (read strobe) mode (maximum speed possible)
#endif
#endif
SEMC_BR0 = (SDRAM_ADDR | SEMC_BR_MS_32MB | SEMC_BR_VLD);
SEMC_IOCR = (SEMC_IOCR_MUX_RDY_NAND_RDY_WAIT | SEMC_IOCR_MUX_CSX3_DBI_CSX
| SEMC_IOCR_MUX_CSX2_NAND_CE | SEMC_IOCR_MUX_CSX1_PSRAM_CE
| SEMC_IOCR_MUX_CSX0_NOR_CE | SEMC_IOCR_MUX_A8_SDRAM_A8);
SEMC_SDRAMCR0 = 0x00000f31;
SEMC_SDRAMCR1 = 0x00652922;
SEMC_SDRAMCR2 = 0x00010920;
SEMC_SDRAMCR3 = 0x50210a08;
SEMC_DBICR0 = 0x00000021;
SEMC_DBICR1 = 0x00888888;
SEMC_IPCR1 = 0x00000002;
SEMC_IPCR2 = 0x00000000;
SEMC_IPCR0 = 0x80000000;
SEMC_IPCMD = (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_PRECHARGE_ALL);
_WAIT_REGISTER_FALSE(SEMC_INTR, SEMC_INTR_IPCMDDONE);
SEMC_IPCR0 = 0x80000000;
SEMC_IPCMD = (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH);
_WAIT_REGISTER_FALSE(SEMC_INTR, SEMC_INTR_IPCMDDONE);
SEMC_IPCR0 = 0x80000000;
SEMC_IPCMD = (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH);
_WAIT_REGISTER_FALSE(SEMC_INTR, SEMC_INTR_IPCMDDONE);
SEMC_IPTXDAT = 0x00000033;
SEMC_IPCR0 = 0x80000000;
SEMC_IPCMD = (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_MODESET);
_WAIT_REGISTER_FALSE(SEMC_INTR, SEMC_INTR_IPCMDDONE);
SEMC_SDRAMCR3 = (0x50210a08 | SEMC_SDRAMCR3_REN);
#endif

#endif

}

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