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STTM STM32 and STR91XF / Re: STR91XF Pre-release
« on: July 13, 2007, 12:44:03 PM »
Update 1: http://www.uTasker.com/software/STR91XF/STR91XF_Update_1.zip
Hi all STR91 users / testers
1. CPU Speed.
To set the PLL speed there are the following defines in app_hw_str91xf.h.
You no doubt know that the STR91 can operate at up to 96MHz. This setting is however for 48MHz operation. The various register settings can be modified to generate various speeds and there is a checking routine which will cause a compile error to be generate if the user tries to set anything with an illegal value (eg. the PLL intermediate frequency must be between within 200 and 622MHz ). See the users’ manual for detail – section 2.4.
To work with 96MHz clock POST_DIVIDE must simply be set to 2 instead of 3.
Note also that when the uTasker simulator is running it displays the exact PLL frequency that the CPU would be running at.
Running at 48MHz is no problem. However to achieve fastest operation there are a number of settings which have to be correct. I have used the ST application note http://www.st.com/stonline/products/literature/an/13563.pdf as reference.
The project does however adapt itself according to the PLL. For example, the PCLK should not be faster than 48MHz and so dividers must be set when the PLL is greater. Then the FLASH wait states has to be increased when operating at over 66MHz. See fnSetFMI() in str91xf.c – here I have had to make a correction so that it operates correctly from bank 0 and bank 1 at all selected speeds.
Then there are some new errata. It is best to collect these from the ST web site. One important point to note is that the original chips (rev. B and D for example) have a problem at 96MHz which means that a reset is only effective when it is a power up reset – this means that debuggers can not really work at 96MHz- check the chips you have on your boards to see whether you have this limitation!! If you do (which is unfortunately very likely), stick to 48MHz for the moment.
There are also some errors (also in the last silicon) to do with clock dividers. In fact I got caught out and I still believe that there is another bug which means that it is in fact necessary to set PCLK to RCLK/8 to get it to divide by 2!! See the following forum discussion for full details about the state of development: http://mcu.st.com/mcu/modules.php?mop=modload&name=Splatt_Forums&file=viewtopic&topic=5460&forum=21
2. PHY. I tested the PHY and found that although it is responding correctly I am not getting the expected interrupt on link up/down. I also found out that the ST PHY doesn’t correspond to the typical PHY register set so I have had to change the defines for it in the header file. This is an open point – see the following forum posting for more details: http://mcu.st.com/mcu/modules.php?mop=modload&name=Splatt_Forums&file=viewtopic&topic=5489&forum=21
However this doesn’t actually affect normal operation – there is just no link up/down events of they were needed.
3. I have added low power support (define SUPPORT_LOW_POWER in config.h) but haven’t actually verified it yet… This uses the IDLE mode of the chip to stop the CPU clock when there is no processing to be performed. As soon as a peripheral interrupt arrives it should continue operation. I have used this successfully with the Coldfire and the SAM7X so I am hoping that it also works well on this chip.
Plan of attack:
- I still have to test the boot loader. The project compiles and I have already successfully used the boot loader with the chip (although not yet over Ethernet).
Since the boot loader occupies only 2k of an 8k FLASH block in Bank 1 I think that it will be useful to add also loading via UART.
- Then I plan to configure a RIDE GNU project (I have successfully used RIDE with the STR91 but it is some time ago and needs main and boot builds).
- Once the RIDE project is good there will be a GNU build but I would then like to use a stand-along GNU build and probably an Eclipse project with it.
If you have any remarks or results from your own tests please let me know.
Thanks for your help.
Best regards
Mark
Hi all STR91 users / testers
1. CPU Speed.
To set the PLL speed there are the following defines in app_hw_str91xf.h.
Code: [Select]
#define CRYSTAL_FREQ 25000000 // crystal or clock input frequency (4 to 25MHz)
#define OSC_DIVIDE 25 // 1..255
#define PLL_MUL 192 // 1..255
#define POST_DIVIDE_EXP 3 // 0..5 (3 for 48MHz, 2 for 96MHz)You no doubt know that the STR91 can operate at up to 96MHz. This setting is however for 48MHz operation. The various register settings can be modified to generate various speeds and there is a checking routine which will cause a compile error to be generate if the user tries to set anything with an illegal value (eg. the PLL intermediate frequency must be between within 200 and 622MHz ). See the users’ manual for detail – section 2.4.
To work with 96MHz clock POST_DIVIDE must simply be set to 2 instead of 3.
Note also that when the uTasker simulator is running it displays the exact PLL frequency that the CPU would be running at.
Running at 48MHz is no problem. However to achieve fastest operation there are a number of settings which have to be correct. I have used the ST application note http://www.st.com/stonline/products/literature/an/13563.pdf as reference.
The project does however adapt itself according to the PLL. For example, the PCLK should not be faster than 48MHz and so dividers must be set when the PLL is greater. Then the FLASH wait states has to be increased when operating at over 66MHz. See fnSetFMI() in str91xf.c – here I have had to make a correction so that it operates correctly from bank 0 and bank 1 at all selected speeds.
Then there are some new errata. It is best to collect these from the ST web site. One important point to note is that the original chips (rev. B and D for example) have a problem at 96MHz which means that a reset is only effective when it is a power up reset – this means that debuggers can not really work at 96MHz- check the chips you have on your boards to see whether you have this limitation!! If you do (which is unfortunately very likely), stick to 48MHz for the moment.
There are also some errors (also in the last silicon) to do with clock dividers. In fact I got caught out and I still believe that there is another bug which means that it is in fact necessary to set PCLK to RCLK/8 to get it to divide by 2!! See the following forum discussion for full details about the state of development: http://mcu.st.com/mcu/modules.php?mop=modload&name=Splatt_Forums&file=viewtopic&topic=5460&forum=21
2. PHY. I tested the PHY and found that although it is responding correctly I am not getting the expected interrupt on link up/down. I also found out that the ST PHY doesn’t correspond to the typical PHY register set so I have had to change the defines for it in the header file. This is an open point – see the following forum posting for more details: http://mcu.st.com/mcu/modules.php?mop=modload&name=Splatt_Forums&file=viewtopic&topic=5489&forum=21
However this doesn’t actually affect normal operation – there is just no link up/down events of they were needed.
3. I have added low power support (define SUPPORT_LOW_POWER in config.h) but haven’t actually verified it yet… This uses the IDLE mode of the chip to stop the CPU clock when there is no processing to be performed. As soon as a peripheral interrupt arrives it should continue operation. I have used this successfully with the Coldfire and the SAM7X so I am hoping that it also works well on this chip.
Plan of attack:
- I still have to test the boot loader. The project compiles and I have already successfully used the boot loader with the chip (although not yet over Ethernet).
Since the boot loader occupies only 2k of an 8k FLASH block in Bank 1 I think that it will be useful to add also loading via UART.
- Then I plan to configure a RIDE GNU project (I have successfully used RIDE with the STR91 but it is some time ago and needs main and boot builds).
- Once the RIDE project is good there will be a GNU build but I would then like to use a stand-along GNU build and probably an Eclipse project with it.
If you have any remarks or results from your own tests please let me know.
Thanks for your help.
Best regards
Mark