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1
NXPTM M522XX, KINETIS and i.MX RT / Re: DIO internal PullDown
« Last post by neil on May 28, 2026, 09:46:06 PM »
Hi Mark,
  I will give that a try. I am using to to read a pin from a modem, the modem keeps this high, then drops to 0 when switched off. But I cant monitor it as always sitting high. I have many units out there now , and would have put a pull down resistor on it but cant get to them. I will just have to use a timeout of these.

Many thanks for your help :)

Best Regards
Neil
2
NXPTM M522XX, KINETIS and i.MX RT / Re: DIO internal PullDown
« Last post by mark on May 28, 2026, 09:33:50 PM »
Hi Neil

I wonder what happens f you connect a 1MOhm resistor to GND from the pin?
If it then goes to '0' it would presumably mean that there is a very low leakage path to 3V but not enough to supply any real current.

Regards

Mark

3
NXPTM M522XX, KINETIS and i.MX RT / Re: DIO internal PullDown
« Last post by neil on May 28, 2026, 06:26:28 PM »
Hi Mark,
  Many thanks for that information. 

Strange though, as when nothing is connected to PA5 (same with a couple of other pins) , it is sitting at 3.3v. 

Best Regards
Neil
4
NXPTM M522XX, KINETIS and i.MX RT / Re: DIO internal PullDown
« Last post by mark on May 28, 2026, 06:04:05 PM »
Hi Neil

Unfortunately AN doesn't have any internal pull-up or pull-down capabilities - see attached image.

Regards

Mark


5
NXPTM M522XX, KINETIS and i.MX RT / DIO internal PullDown
« Last post by neil on May 28, 2026, 02:20:06 PM »
Hi Mark,
  Hope you are doing well..

Its been quite a while since i have done anything on the MFC52259, and dont have anymore much info on programming it. I am wondering if utasker has something I can use   for setting PortA for input and assigning internal pulldown.  Im using the Port A , pin 5 as input as follows:

DDRAN &= ~PORT_AN_BIT5;   //se

if(PORTIN_SETAN & GSM_PWCTRL_PIN)
 ...

But it must be using internal pullups , I really want internal pulldown. Can t add resistor as the units are already in the field.

Many thanks
Neil
6
µTasker general / Re: uTasker Utilities
« Last post by mark on April 25, 2026, 11:42:28 AM »
The utilities run in a Windows environment and require some Microsoft DLLs that are generally present.
In some situations (a new PC which has not had general programs installed yet) the DLLs may be missing.
A typical error message is
"The code excecution cannot proceed because VCRUNTIME140.dll was not found. Reinstalling the program may fix this problem"

If unsure whether this issue is present or not please use the command "uTaskerConvert.exe -v" in a DOS shell to clearly see the result.

In case of this issue existing, the DLL can be installed from
https://learn.microsoft.com/en-us/cpp/windows/latest-supported-vc-redist?view=msvc-170

Note that many programs that are installed will supply the DLL, since they also need it in order to be able to operate, and so it is rare that this is required.
7
NXPTM M522XX, KINETIS and i.MX RT / Re: I sometimes have hard-faults but when they are ignored all work - what is going
« Last post by mark on March 08, 2026, 10:28:59 PM »
Hi

Example: When peripherals are enabled (gated) and then used it is possible that between gating and it being ready there is a delay (in the synchronisation of clock domains) that means that the code using the peripheral will use it slightly too early.
What happens is that there is a hard fault. If the hard fault lands in a forever loop it fails. If the hard fault simply returns it then repeats (and works) and all is fine and it continues.
That is, there can be 'temporary' hard faults that are not really critical.
Often they can be avoided by using instruction / data barrier commands like

asm volatile ("dsb 0xf":::"memory");
asm volatile ("isb 0xf":::"memory");

which cause the processor to wait until the previous peripheral write operations have completed but this can be fiddly.

What I do is use a very simple hard fault handler that counts how often it happens, doesn't result in a loop and recovers (if it is a 'real'/serious hard fault it results in a hard fault interrupt loop anyway, which is very easy to debug as you just need to connect with a debugger and you see the exact code that is faulting (over and over again)).


volatile unsigned long ulHardFaultCounter = 0;
// Serious error interrupts
//
static void irq_hard_fault(void)
{
    ulHardFaultCounter++;                                                // hard faults are often recoverable so we count how many were detected for statistical reasons
}


I can always check the counter value to see whether it does every occasionally happen. If I prefer to 'clean' it up so that it doesn't I just set a break point on the increment line, let it run and see exactly where it takes place and then, if I want, I can add a barrier instruction (or similar - eg. adding some other code before accessing usually works) to exclude it. Recoverable hard faults are however not really worth worrying about as they have no negative side effects (that I ever experienced).

Regards

Mark
8
NXPTM M522XX, KINETIS and i.MX RT / I sometimes have hard-faults but when they are ignored all work - what is going
« Last post by FAQ on March 08, 2026, 10:26:20 PM »
Hi

How can it be that my code hits a hard-fault but, if I let the hard-fault return and not stay in a forever loop, it continues running normally?
9
NXPTM M522XX, KINETIS and i.MX RT / Re: uTasker v2.0.0 doesn't compile on MCUXpresso v11.5.0 (.text LMA overlaps)
« Last post by mark on March 05, 2026, 03:10:58 AM »
Hi

Make sure that you have switched the repo. to V2.0.0 so that you are using newest source (master source will have linker script files that stopped working with newest GCC versions).

When using MCUXpresso the managed build is not used (where the internal settings are configured) but instead the linker script is entered (see the MCUXpresso guide document or video).

I wouldn't bother changing 8M Flash to 4Meg since it won't change anything. It would just give you an error in case >4 Meg was actually used.

Regards

Mark

P.S: Below is the content of \Applications\uTaskerV1.4\GNU_iMX\iMX_RT_10XX_FlexSPI_NOR.ld as reference


======================================================================

/* iMX_RT_10XX_FlexSPI_NOR.ld - compatible with MCUXpresso > V11.4        */
/* GCC memory file for the iMX RT 10XX - for use with the uTasker project */
/* Use when running from FlexSPI Flash (total up to 512k CPU SRAM)        */


_HeapSize = 0x0;                                    /* uTasker project usually does not use library heap */
_StackSize = 0x0;                                   /* uTasker project organises stack at run time       */

MEMORY
{
  /* Define each memory region */
  BOARD_FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 0x800000 /* 8M bytes (alias Flash) */ 
  SRAM_DTC (rwx) : ORIGIN = 0x20000300, LENGTH = 0x80000-0x0300 /* up to 512K bytes (alias RAM) - with vectors at the start */ 
  SRAM_ITC (rwx) : ORIGIN = 0x0, LENGTH = 0x80000 /* up to 512K bytes (alias RAM2) */ 
  SRAM_OC (rwx) : ORIGIN = 0x20200000, LENGTH = 0xc0000 /* 768K bytes (alias RAM3) */ 
  BOARD_SDRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 0x1e00000 /* 30M bytes (alias RAM4) */ 
  NCACHE_REGION (rwx) : ORIGIN = 0x81e00000, LENGTH = 0x200000 /* 2M bytes (alias RAM5) */ 
}

  /* Define a symbol for the top of each memory region */
  __base_BOARD_FLASH = 0x60000000  ; /* BOARD_FLASH */ 
  __base_Flash = 0x60000000 ; /* Flash */ 
  __top_BOARD_FLASH = 0x60000000 + 0x800000 ; /* 8M bytes */ 
  __top_Flash = 0x60000000 + 0x800000 ; /* 8M bytes */ 
  __base_SRAM_DTC = 0x20000300  ; /* SRAM_DTC */ 
  __base_RAM = 0x20000000 ; /* RAM */ 
  __top_SRAM_DTC = 0x20000300 + 0x80000 - 0x0300 ; /* up to 512k bytes */ 
  __top_RAM = 0x20000000 + 0x80000 ; /* up to 512k bytes */ 
  __base_SRAM_ITC = 0x0  ; /* SRAM_ITC */ 
  __base_RAM2 = 0x0 ; /* RAM2 */ 
  __top_SRAM_ITC = 0x0 + 0x80000 ; /* up to 512K bytes */ 
  __top_RAM2 = 0x0 + 0x80000 ; /* up to 512K bytes */ 
  __base_SRAM_OC = 0x20200000  ; /* SRAM_OC */ 
  __base_RAM3 = 0x20200000 ; /* RAM3 */ 
  __top_SRAM_OC = 0x20200000 + 0xc0000 ; /* 768K bytes */ 
  __top_RAM3 = 0x20200000 + 0xc0000 ; /* 768K bytes */ 
  __base_BOARD_SDRAM = 0x80000000  ; /* BOARD_SDRAM */ 
  __base_RAM4 = 0x80000000 ; /* RAM4 */ 
  __top_BOARD_SDRAM = 0x80000000 + 0x1e00000 ; /* 30M bytes */ 
  __top_RAM4 = 0x80000000 + 0x1e00000 ; /* 30M bytes */ 
  __base_NCACHE_REGION = 0x81e00000  ; /* NCACHE_REGION */ 
  __base_RAM5 = 0x81e00000 ; /* RAM5 */ 
  __top_NCACHE_REGION = 0x81e00000 + 0x200000 ; /* 2M bytes */ 
  __top_RAM5 = 0x81e00000 + 0x200000 ; /* 2M bytes */ 



ENTRY(__vector_table)

SECTIONS
{
     /* Image Vector Table and Boot Data for booting from external flash */
    .boot_hdr : ALIGN(4)
    {
        FILL(0xff)
        __boot_hdr_start__ = ABSOLUTE(.) ;
        KEEP(*(.boot_hdr.conf))
        . = 0x1000 ;
        KEEP(*(.boot_hdr.ivt))
        . = 0x1020 ;
        KEEP(*(.boot_hdr.boot_data))
        . = 0x1030 ;
        KEEP(*(.boot_hdr.dcd_data))
        . = 0x1fb0 ;
        KEEP(*(.boot_hdr.key))
        . = 0x1fe0 ;
        KEEP(*(.boot_hdr.init))
        __boot_hdr_end__ = ABSOLUTE(.) ;
        . = 0x2000 ;
    } >BOARD_FLASH

    /* MAIN TEXT SECTION */
    .text : ALIGN(4)
    {
        FILL(0xff)
        __vectors_start__ = ABSOLUTE(.) ;
        KEEP(*(.vectors))
        /* Global Section Table */
        . = ALIGN(4) ;
        __section_table_start = .;
        __data_section_table = .;
        LONG(LOADADDR(.data));
        LONG(    ADDR(.data));
        LONG(  SIZEOF(.data));
        LONG(LOADADDR(.data_RAM2));
        LONG(    ADDR(.data_RAM2));
        LONG(  SIZEOF(.data_RAM2));
        LONG(LOADADDR(.data_RAM3));
        LONG(    ADDR(.data_RAM3));
        LONG(  SIZEOF(.data_RAM3));
        LONG(LOADADDR(.data_RAM4));
        LONG(    ADDR(.data_RAM4));
        LONG(  SIZEOF(.data_RAM4));
        LONG(LOADADDR(.data_RAM5));
        LONG(    ADDR(.data_RAM5));
        LONG(  SIZEOF(.data_RAM5));
        __data_section_table_end = .;
        __bss_section_table = .;
        LONG(    ADDR(.bss));
        LONG(  SIZEOF(.bss));
        LONG(    ADDR(.bss_RAM2));
        LONG(  SIZEOF(.bss_RAM2));
        LONG(    ADDR(.bss_RAM3));
        LONG(  SIZEOF(.bss_RAM3));
        LONG(    ADDR(.bss_RAM4));
        LONG(  SIZEOF(.bss_RAM4));
        LONG(    ADDR(.bss_RAM5));
        LONG(  SIZEOF(.bss_RAM5));
        __bss_section_table_end = .;
        __section_table_end = . ;
        /* End of Global Section Table */

        *(.after_vectors*)

       *(.text*)
       *(.rodata .rodata.* .constdata .constdata.*)
       . = ALIGN(4);
    } > BOARD_FLASH
    /*
     * for exception handling/unwind - some Newlib functions (in common
     * with C++ and STDC++) use this.
     */
    .ARM.extab : ALIGN(4)
    {
        *(.ARM.extab* .gnu.linkonce.armextab.*)
    } > BOARD_FLASH

    .ARM.exidx : ALIGN(4)
    {
        __exidx_start = .;
        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
        __exidx_end = .;
    } > BOARD_FLASH
 
    _etext = .;
       
    /* DATA section for SRAM_ITC */

    .data_RAM2 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM2 = .) ;
        PROVIDE(__start_data_SRAM_ITC = .) ;
        *(.ramfunc.$RAM2)
        *(.ramfunc.$SRAM_ITC)
        *(.data.$RAM2)
        *(.data.$SRAM_ITC)
        *(.data.$RAM2.*)
        *(.data.$SRAM_ITC.*)
        . = ALIGN(4) ;
        PROVIDE(__end_data_RAM2 = .) ;
        PROVIDE(__end_data_SRAM_ITC = .) ;
     } > SRAM_ITC AT>BOARD_FLASH

    /* DATA section for SRAM_OC */

    .data_RAM3 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM3 = .) ;
        PROVIDE(__start_data_SRAM_OC = .) ;
        *(.ramfunc.$RAM3)
        *(.ramfunc.$SRAM_OC)
        *(.data.$RAM3)
        *(.data.$SRAM_OC)
        *(.data.$RAM3.*)
        *(.data.$SRAM_OC.*)
        . = ALIGN(4) ;
        PROVIDE(__end_data_RAM3 = .) ;
        PROVIDE(__end_data_SRAM_OC = .) ;
     } > SRAM_OC AT>BOARD_FLASH

    /* DATA section for BOARD_SDRAM */

    .data_RAM4 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM4 = .) ;
        PROVIDE(__start_data_BOARD_SDRAM = .) ;
        *(.ramfunc.$RAM4)
        *(.ramfunc.$BOARD_SDRAM)
        *(.data.$RAM4)
        *(.data.$BOARD_SDRAM)
        *(.data.$RAM4.*)
        *(.data.$BOARD_SDRAM.*)
        . = ALIGN(4) ;
        PROVIDE(__end_data_RAM4 = .) ;
        PROVIDE(__end_data_BOARD_SDRAM = .) ;
     } > BOARD_SDRAM AT>BOARD_FLASH

    /* DATA section for NCACHE_REGION */

    .data_RAM5 : ALIGN(4)
    {
        FILL(0xff)
        PROVIDE(__start_data_RAM5 = .) ;
        PROVIDE(__start_data_NCACHE_REGION = .) ;
        *(.ramfunc.$RAM5)
        *(.ramfunc.$NCACHE_REGION)
        *(.data.$RAM5)
        *(.data.$NCACHE_REGION)
        *(.data.$RAM5.*)
        *(.data.$NCACHE_REGION.*)
        . = ALIGN(4) ;
        PROVIDE(__end_data_RAM5 = .) ;
        PROVIDE(__end_data_NCACHE_REGION = .) ;
     } > NCACHE_REGION AT>BOARD_FLASH

    /* MAIN DATA SECTION */
    .uninit_RESERVED (NOLOAD) : ALIGN(4)
    {
        _start_uninit_RESERVED = .;
        KEEP(*(.bss.$RESERVED*))
       . = ALIGN(4) ;
        _end_uninit_RESERVED = .;
    } > SRAM_DTC AT> SRAM_DTC

    /* Main DATA section (SRAM_DTC) */
    .data : ALIGN(4)
    {
       FILL(0xff)
       _data = . ;
       PROVIDE(__start_data_RAM = .) ;
       PROVIDE(__start_data_SRAM_DTC = .) ;
       *(vtable)
       *(.ramfunc*)
       KEEP(*(CodeQuickAccess))
       KEEP(*(DataQuickAccess))
       *(RamFunction)
       *(NonCacheable.init)
       *(.data*)
       . = ALIGN(4) ;
       _edata = . ;
       PROVIDE(__end_data_RAM = .) ;
       PROVIDE(__end_data_SRAM_DTC = .) ;
    } > SRAM_DTC AT>BOARD_FLASH

    /* BSS section for SRAM_ITC */
    .bss_RAM2 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM2 = .) ;
       PROVIDE(__start_bss_SRAM_ITC = .) ;
       *(.bss.$RAM2)
       *(.bss.$SRAM_ITC)
       *(.bss.$RAM2.*)
       *(.bss.$SRAM_ITC.*)
       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM2 = .) ;
       PROVIDE(__end_bss_SRAM_ITC = .) ;
    } > SRAM_ITC AT> SRAM_ITC

    /* BSS section for SRAM_OC */
    .bss_RAM3 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM3 = .) ;
       PROVIDE(__start_bss_SRAM_OC = .) ;
       *(.bss.$RAM3)
       *(.bss.$SRAM_OC)
       *(.bss.$RAM3.*)
       *(.bss.$SRAM_OC.*)
       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM3 = .) ;
       PROVIDE(__end_bss_SRAM_OC = .) ;
    } > SRAM_OC AT> SRAM_OC

    /* BSS section for BOARD_SDRAM */
    .bss_RAM4 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM4 = .) ;
       PROVIDE(__start_bss_BOARD_SDRAM = .) ;
       *(.bss.$RAM4)
       *(.bss.$BOARD_SDRAM)
       *(.bss.$RAM4.*)
       *(.bss.$BOARD_SDRAM.*)
       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM4 = .) ;
       PROVIDE(__end_bss_BOARD_SDRAM = .) ;
    } > BOARD_SDRAM AT> BOARD_SDRAM

    /* BSS section for NCACHE_REGION */
    .bss_RAM5 : ALIGN(4)
    {
       PROVIDE(__start_bss_RAM5 = .) ;
       PROVIDE(__start_bss_NCACHE_REGION = .) ;
       *(.bss.$RAM5)
       *(.bss.$NCACHE_REGION)
       *(.bss.$RAM5.*)
       *(.bss.$NCACHE_REGION.*)
       . = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
       PROVIDE(__end_bss_RAM5 = .) ;
       PROVIDE(__end_bss_NCACHE_REGION = .) ;
    } > NCACHE_REGION AT> NCACHE_REGION

    /* MAIN BSS SECTION */
    .bss : ALIGN(4)
    {
        _bss = .;
        PROVIDE(__start_bss_RAM = .) ;
        PROVIDE(__start_bss_SRAM_DTC = .) ;
       *(NonCacheable)
        *(.bss*)
        *(COMMON)
        . = ALIGN(4) ;
        _ebss = .;
        PROVIDE(__end_bss_RAM = .) ;
        PROVIDE(__end_bss_SRAM_DTC = .) ;
        PROVIDE(end = .);
    } > SRAM_DTC AT> SRAM_DTC

    /* NOINIT section for SRAM_ITC */
    .noinit_RAM2 (NOLOAD) : ALIGN(4)
    {
       PROVIDE(__start_noinit_RAM2 = .) ;
       PROVIDE(__start_noinit_SRAM_ITC = .) ;
       *(.noinit.$RAM2)
       *(.noinit.$SRAM_ITC)
       *(.noinit.$RAM2.*)
       *(.noinit.$SRAM_ITC.*)
       . = ALIGN(4) ;
       PROVIDE(__end_noinit_RAM2 = .) ;
       PROVIDE(__end_noinit_SRAM_ITC = .) ;
    } > SRAM_ITC AT> SRAM_ITC

    /* NOINIT section for SRAM_OC */
    .noinit_RAM3 (NOLOAD) : ALIGN(4)
    {
       PROVIDE(__start_noinit_RAM3 = .) ;
       PROVIDE(__start_noinit_SRAM_OC = .) ;
       *(.noinit.$RAM3)
       *(.noinit.$SRAM_OC)
       *(.noinit.$RAM3.*)
       *(.noinit.$SRAM_OC.*)
       . = ALIGN(4) ;
       PROVIDE(__end_noinit_RAM3 = .) ;
       PROVIDE(__end_noinit_SRAM_OC = .) ;
    } > SRAM_OC AT> SRAM_OC

    /* NOINIT section for BOARD_SDRAM */
    .noinit_RAM4 (NOLOAD) : ALIGN(4)
    {
       PROVIDE(__start_noinit_RAM4 = .) ;
       PROVIDE(__start_noinit_BOARD_SDRAM = .) ;
       *(.noinit.$RAM4)
       *(.noinit.$BOARD_SDRAM)
       *(.noinit.$RAM4.*)
       *(.noinit.$BOARD_SDRAM.*)
       . = ALIGN(4) ;
       PROVIDE(__end_noinit_RAM4 = .) ;
       PROVIDE(__end_noinit_BOARD_SDRAM = .) ;
    } > BOARD_SDRAM AT> BOARD_SDRAM

    /* NOINIT section for NCACHE_REGION */
    .noinit_RAM5 (NOLOAD) : ALIGN(4)
    {
       PROVIDE(__start_noinit_RAM5 = .) ;
       PROVIDE(__start_noinit_NCACHE_REGION = .) ;
       *(.noinit.$RAM5)
       *(.noinit.$NCACHE_REGION)
       *(.noinit.$RAM5.*)
       *(.noinit.$NCACHE_REGION.*)
       . = ALIGN(4) ;
       PROVIDE(__end_noinit_RAM5 = .) ;
       PROVIDE(__end_noinit_NCACHE_REGION = .) ;
    } > NCACHE_REGION AT> NCACHE_REGION

    /* DEFAULT NOINIT SECTION */
    .noinit (NOLOAD): ALIGN(4)
    {
        _noinit = .;
        PROVIDE(__start_noinit_RAM = .) ;
        PROVIDE(__start_noinit_SRAM_DTC = .) ;
        *(.noinit*)
         . = ALIGN(4) ;
        _end_noinit = .;
       PROVIDE(__end_noinit_RAM = .) ;
       PROVIDE(__end_noinit_SRAM_DTC = .) ;       
    } > SRAM_DTC AT> SRAM_DTC

    /* Reserve and place Heap within memory map */
    .heap (NOLOAD) :  ALIGN(4)
    {
        _pvHeapStart = .;
        . += _HeapSize;
        . = ALIGN(4);
        _pvHeapLimit = .;
    } > SRAM_DTC

     /* Reserve space in memory for Stack */
    .heap2stackfill (NOLOAD) :
    {
        . += _StackSize;
    } > SRAM_DTC
    /* Locate actual Stack in memory map */
    .stack ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - _StackSize - 0 (NOLOAD) :  ALIGN(4)
    {
        _vStackBase = .;
        . = ALIGN(4);
        _vStackTop = . + _StackSize;
    } > SRAM_DTC

    /* Provide basic symbols giving location and size of main text
     * block, including initial values of RW data sections. Note that
     * these will need extending to give a complete picture with
     * complex images (e.g multiple Flash banks).
     */
    _image_start = LOADADDR(.text);
    _image_end = LOADADDR(.data) + SIZEOF(.data);
    _image_size = _image_end - _image_start;

    /* For compatibility with uTasker names */
    /*                                      */
    __data_start__ = _start_uninit_RESERVED;
    __data_end__ = __data_start__ + SIZEOF(.data);
    __data_load_start__ = LOADADDR (.data);
    __bss_start__ = __start_bss_RAM;
    __bss_end__ = __start_bss_RAM + SIZEOF(.bss);
    __heap_end__ = _pvHeapLimit;
}
10
NXPTM M522XX, KINETIS and i.MX RT / Re: uTasker v2.0.0 doesn't compile on MCUXpresso v11.5.0 (.text LMA overlaps)
« Last post by lolachampcar on March 04, 2026, 12:06:05 AM »
Mark,

Sorry to ressurect an old thread but I too am getting the

D:/nxp/MCUXpressoIDE_25.6.136/ide/plugins/com.nxp.mcuxpresso.tools.win32_25.6.0.202501151204/tools/bin/../lib/gcc/arm-none-eabi/14.2.1/../../../../arm-none-eabi/bin/ld.exe: section .text LMA [60000000,60001b8b] overlaps section .text LMA [60000000,60001fff]
D:/nxp/MCUXpressoIDE_25.6.136/ide/plugins/com.nxp.mcuxpresso.tools.win32_25.6.0.202501151204/tools/bin/../lib/gcc/arm-none-eabi/14.2.1/../../../../arm-none-eabi/bin/ld.exe: section .rodata LMA [60000000,60000029] overlaps section .text LMA [60000000,60001b8b]
 
overlap error while trying to build uTasker1 master is MCUXpresso V25.6.  I've copied the .ld files I downloaded from the thread referenced in your post above and placed them in the appropriate directory to no affect.  Can you please advise on other corrective measures.

On a related note, I've configured the project for a 4mb flash (see attached) yet the build results are still saying 8mb.  Is there another configuration change required?

Memory region         Used Size  Region Size  %age Used
       SPI_FLASH:        8200 B         8 MB      0.10%
        SRAM_DTC:           0 B     523520 B      0.00%
        SRAM_ITC:           0 B       512 KB      0.00%
         SRAM_OC:           0 B       512 KB      0.00%
     BOARD_SDRAM:           0 B        32 MB      0.00%



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