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31
NXPTM M522XX, KINETIS and i.MX RT / Re: Serial Loader: Placing vars into SDRAM?
« Last post by jackking on February 09, 2024, 02:38:49 PM »
OK, I have created my own SEMC init function (from the code in glcd_tft.h) and that seems to work.  This would seem to indicate that either the DCD data is not correct or not getting applied in the uTaskerBoot code...

Here is the SEMC init code I am using:

Code: [Select]
void fnInitSEMC(void) {

#if (defined MIMXRT1050 || defined iMX_RT1052_EMB_ART || defined iMX_RT1062_EMB_ART || defined MIMXRT1060  || defined MIMXRT1064) // {8}

#if (!defined SDRAM_CONFIGURED_BY_DCD)
// Configure SEMC pins and SDRAM (IS42S16160J-6BLI)
//
_CONFIG_PERIPHERAL(GPIO_EMC_00, SEMC_DATA00,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA00 on GPIO4-00 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_01, SEMC_DATA01,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA01 on GPIO4-01 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_02, SEMC_DATA02,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA02 on GPIO4-02 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_03, SEMC_DATA03,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA03 on GPIO4-03 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_04, SEMC_DATA04,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA04 on GPIO4-04 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_05, SEMC_DATA05,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA05 on GPIO4-05 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_06, SEMC_DATA06,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA06 on GPIO4-06 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_07, SEMC_DATA07,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA07 on GPIO4-07 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_30, SEMC_DATA08,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA08 on GPIO4-30 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_31, SEMC_DATA09,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA09 on GPIO4-31 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_32, SEMC_DATA10,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA10 on GPIO3-18 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_33, SEMC_DATA11,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA11 on GPIO3-19 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_34, SEMC_DATA12,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA12 on GPIO3-20 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_35, SEMC_DATA13,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA13 on GPIO3-21 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_36, SEMC_DATA14,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA14 on GPIO3-22 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_37, SEMC_DATA15,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DATA15 on GPIO3-23 - alt function 0 (direction input/output)
_CONFIG_PERIPHERAL(GPIO_EMC_09, SEMC_ADDR00,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR00 on GPIO4-09 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_10, SEMC_ADDR01,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR01 on GPIO4-10 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_11, SEMC_ADDR02,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR02 on GPIO4-11 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_12, SEMC_ADDR03,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR03 on GPIO4-12 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_13, SEMC_ADDR04,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR04 on GPIO4-13 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_14, SEMC_ADDR05,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR05 on GPIO4-14 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_15, SEMC_ADDR06,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR06 on GPIO4-15 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_16, SEMC_ADDR07,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR07 on GPIO4-16 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_17, SEMC_ADDR08,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR08 on GPIO4-17 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_18, SEMC_ADDR09,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR09 on GPIO4-18 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_23, SEMC_ADDR10,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR10 on GPIO4-23 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_19, SEMC_ADDR11,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR11 on GPIO4-19 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_20, SEMC_ADDR12,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_ADDR12 on GPIO4-20 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_21, SEMC_BA0,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_BA0 on GPIO4-21 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_22, SEMC_BA1,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_BA1 on GPIO4-22 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_24, SEMC_CAS,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_CAS on GPIO4-24 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_25, SEMC_RAS,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_RAS on GPIO4-25 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_26, SEMC_CLK,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_CLK on GPIO4-26 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_27, SEMC_CKE,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_CKE on GPIO4-27 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_28, SEMC_WE,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_WE on GPIO4-28 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_29, SEMC_CS0,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_CS0 on GPIO4-29 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_08, SEMC_DM00,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DM00 on GPIO4-08 - alt function 0 (direction output)
_CONFIG_PERIPHERAL(GPIO_EMC_38, SEMC_DM01,
(IOMUXC_SW_PAD_CTL_PAD_HYS | IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MAX | IOMUXC_SW_PAD_CTL_PAD_DSE_7 | IOMUXC_SW_PAD_CTL_PAD_SRE)); // select SEMC_DM01 on GPIO3-24 - alt function 0 (direction output)
POWER_UP_ATOMIC(1, SEMC_EXSC_CLOCK);
POWER_UP_ATOMIC(3, SEMC_CLOCKS);
#if defined iMX_RT1062
#if defined APPLICATION_REQUIRES_GPIO_EMC_39
SEMC_MCR = 0; // dummy read strobe loop backed internally - maximum 60MHz operation
#else
SEMC_MCR = (SEMC_MCR_BTO_DEFAULT | SEMC_MCR_DQSMD); // DQS (read strobe) mode (maximum speed possible)
#endif
#else
#if defined APPLICATION_REQUIRES_GPIO_EMC_39
SEMC_MCR = 0; // dummy read strobe loop backed internally - maximum 60MHz operation
#else
SEMC_MCR = (SEMC_MCR_DQSMD); // DQS (read strobe) mode (maximum speed possible)
#endif
#endif
SEMC_BR0 = (SDRAM_ADDR | SEMC_BR_MS_32MB | SEMC_BR_VLD);
SEMC_IOCR = (SEMC_IOCR_MUX_RDY_NAND_RDY_WAIT | SEMC_IOCR_MUX_CSX3_DBI_CSX
| SEMC_IOCR_MUX_CSX2_NAND_CE | SEMC_IOCR_MUX_CSX1_PSRAM_CE
| SEMC_IOCR_MUX_CSX0_NOR_CE | SEMC_IOCR_MUX_A8_SDRAM_A8);
SEMC_SDRAMCR0 = 0x00000f31;
SEMC_SDRAMCR1 = 0x00652922;
SEMC_SDRAMCR2 = 0x00010920;
SEMC_SDRAMCR3 = 0x50210a08;
SEMC_DBICR0 = 0x00000021;
SEMC_DBICR1 = 0x00888888;
SEMC_IPCR1 = 0x00000002;
SEMC_IPCR2 = 0x00000000;
SEMC_IPCR0 = 0x80000000;
SEMC_IPCMD = (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_PRECHARGE_ALL);
_WAIT_REGISTER_FALSE(SEMC_INTR, SEMC_INTR_IPCMDDONE);
SEMC_IPCR0 = 0x80000000;
SEMC_IPCMD = (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH);
_WAIT_REGISTER_FALSE(SEMC_INTR, SEMC_INTR_IPCMDDONE);
SEMC_IPCR0 = 0x80000000;
SEMC_IPCMD = (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_AUTO_REFRESH);
_WAIT_REGISTER_FALSE(SEMC_INTR, SEMC_INTR_IPCMDDONE);
SEMC_IPTXDAT = 0x00000033;
SEMC_IPCR0 = 0x80000000;
SEMC_IPCMD = (SEMC_IPCMD_KEY | SEMC_IPCMD_SDRAM_MODESET);
_WAIT_REGISTER_FALSE(SEMC_INTR, SEMC_INTR_IPCMDDONE);
SEMC_SDRAMCR3 = (0x50210a08 | SEMC_SDRAMCR3_REN);
#endif

#endif

}
32
NXPTM M522XX, KINETIS and i.MX RT / Re: Serial Loader: Placing vars into SDRAM?
« Last post by jackking on February 08, 2024, 04:05:28 PM »
I tried recreating the DCD data using the values from NXP, but this didn't really help.   I still get the same result. 

I will try next to use the NXP iMXRT1052 EVK, also try setting up the SEMC in the application directly vs relying on the DCD, but this will take some time to set up.

@mark.  Do you have a project that is validated to work with the SDRAM on i.MX RT?    I am just building the project with very few modifications and it isn't working.

Thanks
JK

33
NXPTM M522XX, KINETIS and i.MX RT / Re: Serial Loader: Placing vars into SDRAM?
« Last post by jackking on February 07, 2024, 03:22:51 PM »
I cloned a new checkout from the V2.0.0 branch, and built from scratch, with the only change to add the SDRAM test routine shown above and remove the #define for REV_C and add the define for SDRAM support. 

It still crashes after writing 32 bytes.

This is building for iMX_RT1062_EMB_ART,  Rev B, not Rev C, so I have commented out the define for Rev C:
Code: [Select]
//#define iMX_RT10XX_EMB_ART_REV_C
#define BOOT_LOADER_SUPPORTS_SDRAM

Building in MCUXpresso 11.4.1_6260 so I don't need to modify the linker scripts.

Here is the test output:
Code: [Select]
uTasker Serial Loader V2.4                                                     
===========================                                                     
[0x60020100/0x6009ffff]                                                         
bc = blank check                                                               
dc = delete code                                                               
ld = start load                                                                 
bt = start boot loader                                                         
go = start application                                                         
> Enumerated                                                                   
rd                                                                             
Write SDRAM: .................................   

After writing  those bytes the application crashes and the watchdog resets.

I'm not sure where to go from here. 

Thanks
JK
34
NXPTM M522XX, KINETIS and i.MX RT / Re: Serial Loader: Placing vars into SDRAM?
« Last post by jackking on February 06, 2024, 05:58:41 PM »
OK, I have rolled my code back as far as possible to the latest V2.0.0 master commit and I still get the same behaviour with SDRAM.  I am going to try on my Embedded Artists dev kit next.

Thanks
JK
35
NXPTM M522XX, KINETIS and i.MX RT / Re: Serial Loader: Placing vars into SDRAM?
« Last post by jackking on February 06, 2024, 01:00:33 AM »
OK, that is similar to what I tried, without success. 

I set the following in config.h of uTaskerBoot:
Code: [Select]
#define BOOT_LOADER_SUPPORTS_SDRAM
I set the following in app_hw_iMX.h of uTaskerSerialBoot:

Code: [Select]
    #define SDRAM_SIZE          (32 * 1024 * 1024)                       // 32MByte
    #define BOOT_LOADER_SUPPORTS_SDRAM
    #define SDRAM_START_ADDRESS     0x80000000
    #define DISABLE_SDRAM_CACHE
    #define SEMC_AVAILABLE

and added your routine as a menu item under "rd" for RAM DUMP:
Code: [Select]
else if ((ucSerialDebugInputMessage[0] == 'r')
|| (ucSerialDebugInputMessage[0] == 'R')) {
if ((ucSerialDebugInputMessage[1] == 'd')
|| (ucSerialDebugInputMessage[1] == 'D')) {

fnDebugMsg("\r\nWrite SDRAM: ");
unsigned char *ptrSDRAM = (unsigned char *)SDRAM_ADDR;
unsigned long ulTestCnt = (4 * 1024 * 1024);
unsigned char ucByte = 0;
while (ulTestCnt--  != 0) {
    *ptrSDRAM++ = ucByte++;
}

fnDebugMsg("\r\nDump SDRAM: ");
ptrSDRAM = (unsigned char *)SDRAM_ADDR;
ulTestCnt = (4 * 1024 * 1024);
while (ulTestCnt--  != 0) {
    fnDebugHex((unsigned char) *ptrSDRAM++, (sizeof(unsigned char)));
}

break;
}
}

Which instantly crashes when trying to write past 0x20 bytes.  It also crashes immediately on the read back of the first byte, if I write less than 0x20 bytes.
36
NXPTM M522XX, KINETIS and i.MX RT / Re: Serial Loader: Placing vars into SDRAM?
« Last post by mark on February 05, 2024, 11:09:40 PM »
Hi

If you enable
#define BOOT_LOADER_SUPPORTS_SDRAM                   // enable when the boot loader is to configure SDRAM for subsequent application use (or when application runs in SDRAM)
when building the primary loader the SDRAM can be used by the serial loader or the application without needing to configure there.

The SDRAM is located at 0x80000000 [SDRAM_ADDR] and so the easiest way to store data to is to use a pointer as follows:

Code: [Select]
unsigned char *ptrSDRAM = (unsigned char *)SDRAM_ADDR;
unsigned char ucByte = 0;
unsigned long ulTestCnt = (4 * 1024 * 1024);
while (ulTestCnt--  != 0) {
    *ptrSDRAM++ = ucByte++;
}
which should, as example,  leave a 0x00, 0x01, 0x02... pattern throughout 4Meg of the SDRAM.

Regards

Mark
37
NXPTM M522XX, KINETIS and i.MX RT / Serial Loader: Placing vars into SDRAM?
« Last post by jackking on February 05, 2024, 04:01:48 PM »
I am trying to figure out how to place a file buffer into i.MX RT SDRAM in the Serial Loader application.   I am receiving my (binary, not SREC) update file via slow UART and would like to capture the entire file into a buffer (4MB) before erasing and then flashing XiP memory.

Is there an example of placing a specific var into SDRAM memory?

Thanks
JK
38
NXPTM M522XX, KINETIS and i.MX RT / i.MX RT Guide to Setting Peripheral Functions
« Last post by mark on January 24, 2024, 08:26:01 PM »
Hi All

This example shows how to configure a peripheral pin with help if the _CONFIG_PERIPHERAL() or _CONFIG_PERIPHERAL_LOOPBACK() macros.

As an example I will configure LPSPI3_SCK function on the pin referenced as GPIO_AD_B1_15 (assuming an i.MX RT 106x)


This is the code:

IOMUXC_LPSPI3_SCK_SELECT_INPUT = IOMUXC_LPSPI3_SCK_SELECT_INPUT_GPIO_AD_B1_15_ALT2;
_CONFIG_PERIPHERAL_LOOPBACK(GPIO_AD_B1_15, LPSPI3_SCK, (IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MEDIUM | IOMUXC_SW_PAD_CTL_PAD_DSE_6));


and this is how one arrives at it:

1. One needs to know which GPIO reference (PAD) it is on -> GPIO_AD_B1_15 in this case

2. One searches for this in iMX.h until one finds the list of mux options belonging to it

    #define GPIO_AD_B1_15_FLEXSPIA_SS0_B           (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT0)
    #define GPIO_AD_B1_15_ACMP_OUT03               (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT1)
    #define GPIO_AD_B1_15_LPSPI3_SCK               (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT2)
    #define GPIO_AD_B1_15_SAI1_TX_SYNC             (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT3)
    #define GPIO_AD_B1_15_CSI_DATA02               (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT4)
    #define GPIO_AD_B1_15_GPIO1_IO31               (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT5)
    #define GPIO_AD_B1_15_USDHC2_DATA7             (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT6)
    #define GPIO_AD_B1_15_KPP_COL00                (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT7)
    #if defined iMX_RT106X
        #define GPIO_AD_B1_15_ENET2_1588_EVENT3_IN (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT8)
        #define GPIO_AD_B1_15_FLEXIO3_FLEXIO15     (IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_ALT9)
    #endif



3. One take the full mux name (GPIO_AD_B1_15_LPSPI3_SCK) and insert it into the macro, with a comma separating the GPIO reference and the peripheral mux reference belonging to that GPIO:

 _CONFIG_PERIPHERAL_LOOPBACK(GPIO_AD_B1_15, LPSPI3_SCK, (IOMUXC_SW_PAD_CTL_PAD_PKE | IOMUXC_SW_PAD_CTL_PAD_SPEED_MEDIUM | IOMUXC_SW_PAD_CTL_PAD_DSE_6));


This can't be done wrong since it will not compile if incorrect GPIOs aad peripherals are attempted.
The characteristics (last parameter) can be modified to control drive strength and slew rate, etc.

4. Note that either _CONFIG_PERIPHERAL() or _CONFIG_PERIPHERAL_LOOPBACK() is used.
The first is used in most cases but the _CONFIG_PERIPHERAL_LOOPBACK() one is needed for some signals that are generated to be driven onto the pin and also need to be looped back internally to be driven to the peripheral itself. In the case of the LPSPI master operation this MUST be used for the CLK otherwise the clock will be generated but not be connected internally, meaning it won't work completely.

5. Some peripheral pins need an additional sub-muxing setting since they can be located on multiple pins.

IOMUXC_LPSPI3_SCK_SELECT_INPUT = IOMUXC_LPSPI3_SCK_SELECT_INPUT_GPIO_AD_B1_15_ALT2;

To see whether it is necessary it is easiest to search iMX.h for IOMUXC_x (where x is the name of the peripheral signal) -> IOMUXC_LPSPI3_SCK
If it shows up as a IOMUX_xxxx_SELECT_INPUT register, like:

    #define IOMUXC_LPSPI3_SCK_SELECT_INPUT             *(unsigned long *)(IOMUXC_SW_BLOCK + 0x0510) // LPSPI3_SCK_SELECT_INPUT DAISY register
        #define IOMUXC_LPSPI3_SCK_SELECT_INPUT_GPIO_AD_B0_00_ALT7 0x00000000 // select GPIO_AD_B0_00 for mode: ALT7
        #define IOMUXC_LPSPI3_SCK_SELECT_INPUT_GPIO_AD_B1_15_ALT2 0x00000001 // select GPIO_AD_B1_15 for mode: ALT2


it should be set.

IOMUXC_LPSPI3_SCK_SELECT_INPUT = IOMUXC_LPSPI3_SCK_SELECT_INPUT_GPIO_AD_B1_15_ALT2;



One can get away without setting it in case the 0x00000000 is true since it defaults to that, but as good practice it is best to always set the value. It also means that when modifying such configurations one doesn't forget to check and set the value accordingly.

If there is no corresponding IOMUXC_xxxxx_SELECT_INPUT register there is no sub-mux setting to be made.


6. After making such changes one can run the simulator and hover the mouse over the pins one wants to check and it will show the present GPIO/peripheral function so one can easily verify that it is correct before testing on HW.



Regards

Mark
39
NXPTM M522XX, KINETIS and i.MX RT / Re: Compiler Issue
« Last post by mark on January 24, 2024, 08:13:58 PM »
Hi Neil

I have attached the missing folder as zip file.

Regards

Mark
40
NXPTM M522XX, KINETIS and i.MX RT / Re: Compiler Issue
« Last post by neil on January 22, 2024, 07:17:56 PM »
Hi Mark,
  My version doesnt have a CW10 project, would it be possible to get a copy of this?

Best Regards
Neil
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