Hi All
Testing an M52259 project today using CW7.2 I realised that the UART receiver interrupt had stopped working correctly.
The reason was that when transmission is completed the transmit interrupt was being disabled; during the transmit disable process the receiver interrupt enable was also being cleared. This turned out to be a compiler error with CW7.2 - presumably only when optimisation is enabled.
The original code in the routine extern void fnClearTxInt(QUEUE_HANDLE Channel) in M5223X.c was:
unsigned char ucEnabled = (ucEnabledState[Channel] &= ~UART_TXRDY_MASK); // we must make a backup since the register cannot be read
...
*ptrReg = ucEnabled; // disable the interrupt
This means that the transmitter interrupt bit is cleared in the interrup mask backup and then the new result written to the register (ptrReg is pointing to UIMR_UISR_0)
The problem was found to be that the bit was correctly being cleared in RAM by loading 0 to the CPU register and then performing a bit clear directly to the RAM location. But the regiszer d2 (with value 0) was then being written to the interrupt mask register, thus clearing also the rx interrupt mask bit.
The workaround is as follows:
unsigned char ucEnabled;
ucEnabledState[Channel] &= ~UART_TXRDY_MASK;
ucEnabled = ucEnabledState[Channel];
...
*ptrReg = ucEnabled; // disable the interrupt
The code is effectively the same but the result is now as expected, and as it has been with previous CW versions.
Regards
Mark
