Kinetis PWM frequency

[boredman]

While playing with PWM on Teensy 3.6, I discovered that PWM frequency is half of what I wanted it to be. I think I traced the source of the problem to this code in kinetis_PWM.h:

Code: [Select]

            if ((ulMode & PWM_POLARITY) != 0) {                          // polarity
                ptrFlexTimer->FTM_channel[ucChannel].FTM_CSC = FTM_CSC_MS_ELS_PWM_LOW_TRUE_PULSES;
            }
            else {
                ptrFlexTimer->FTM_channel[ucChannel].FTM_CSC = FTM_CSC_MS_ELS_PWM_HIGH_TRUE_PULSES;
            }
            //
            ptrFlexTimer->FTM_channel[ucChannel].FTM_CSC = (FTM_CSC_ELSA | FTM_CSC_MSA);
            //

I do not understand the intention of the last line, but it seems that it configures the mode to Output Compare, thus overwriting the line before. Was this intended?

If I comment out the last line, the PWM frequency is correct.

Thanks for your help!

[mark]

Hi

That line of code was used to test something and unfortunately left in. Therefore it is correct to comment it out (or remove it). This was so in the Open Source version but not the developer's version.

I'll be making a check-in shortly of the Open Source version with new tinyK22 target and MQTT protocol where this will be corrected.

Regards

Mark

[boredman]

Thanks Mark!

One more thing, if I'm not mistaken, in kinetis.h PWM_CLOCK should be (BUS_CLOCK) and not (SYSTEM_CLOCK/2). I found this after setting 180MHz core clock through USE_HIGH_SPEED_RUN_MODE.

Could you please confirm?

[mark]

Hi

You are correct, PWM_CLOCK should be BUS_CLOCK for the K66 (and other K parts).

I think that there was once confusion with the fact that the user manuals all state that the (standard) clock source for the FlexTimer is the system clock. However, it was found that the speed obtained was half that expected (generally one runs the bus clock half the speed of the system clock) and so I expect a divide by 2 was added to get it to match and it stuck there.

Only when the ratio of system clock to bus clock is changed (as in the case of running the K66 at 180MHz core/system speed whereby the fastest bus speed of 60MHz means that a 1/3 ratio is used instead) does one notice a discrepancy.

Looking at a different section of the manual where there is a list of bus interface clock sources  to each module the "bus clock" is indeed specified.

Thanks - I have corrected this after a couple of verification tests.

Regards

Mark