83640 PHY

[emussini]

Hi, we have built our design based on the 52259EVB from Freescale, but unfortunately we can not get the 83640 PHY from National to report ethernet link. This problem is probably not realted to uTasker, but any help would be appreciated.

We have built three prototypes with similar results:

a. No ethernet link at all in 100Mb mode.
b. If we force 10Mb mode by writing to the 0x0 register in the PHY and force the PC's network card to 10BaseT, the pc reports link, but our design doesnt.
c. We checked straps, reset and clock (25mhz) to be ok in the 83640.
d. We compared waveforms in our design and in the EBV and found that TX_CLK and RX_CLK signals in the 83640 are 50mhz with lots of jitter instead of the 25 Mhz required for the part to run in 100Mb mode. Also in 10Mb mode, frequency is 5Mhz instead of 2.5Mhz
e. The normal Link pulse sent every 16ms is 50ns instead of 100.
f. We compared all the 83640 registers in our design with the registers in a running EBV board, and the contents are identical!

We tried several prototypes with and without the 82259  installed and observed similar results. We were wondering if anybody designed based on the 82259 EVB board and had similar problems, or maybe can suggest an approach for debugging this problem.

Thanks for your time

Elio Mussini

[mark]

Hi Elio

Is the PHY somehow trying to operate in RMII mode? RMII mode requires a 50MHz clock rather than 25MHz - maybe the PHY has a PLL to achieve this and so is doubling frequencies?

I haven't studied this PHY because it is quite an exotic type (expensive in comparison to simpler ones) - I think due to its IEEE 1588 capabilities. I do have the M52259EVB but, as you know, this operates 'normally'.

Regards

Mark

[emussini]

Hi Mark, thanks for your suggestion. Indeed that's what I thought in the beginning. To investigate this, I wrote a small program to dump all the internal MII register contents. Unfortunately I see no indication in the registers that the part is runing in RMII mode, even worst, the register dump is exacly the same when I run the code in a working 52259EVB board. You are right about internal clock generation, I replaced the 25mhz crystal with a 12 mhz  and the TX_CLK still oscillates at 50mhz!
Also, why the part would use RMII mode? all straps are according to the 52259EVB design. Can't really figure out whats wrong.

Thanks again for your time

Elio

[emussini]

Mark, I just tested straps to enter RMII mode, the 83640 in my board does it with no problem. If I read PHY register 0x17 I get bit 5 on indicating RMII slave mode. In this situation I dont see any activity in TX_CLK. As soon as I CLR bit 5, to enter into standard MII mode I see the 50 mhz again in TX_CLK.

Elio

[mark]

Hi Elio

Your case is clearly difficult since the configuration of the PHY seems fine (strapping sometimes gives some problems but there is no indication of this).

Have you done comparisons without the Ethernet transformer in place? It's a shot in the dark but maybe the PHY behaves differently with different magnetic/loading (?)

It will probably not help, but I once have difficulties with a board with Ethernet/PHY and, although things looked good, it just didn't want to communicate. It turned out to be the fact that the circuit was designed for a PHY plus a discrete transformer plus an Ethernet socket (three components) but the Ethernet socket put onto the prototypes actually had an internal transformer too. This took some time to realise and then, after changing it for a simple socket without internal magnetics, all problems disappeared.

Regards

Mark