Hi
I believe that the problem is that you have
#define CLOCK_DIV 2
This means that your 8MHz crystal is divided to 4MHz before the PLL. This is out of specification for the 20FX512, which should have an input reference frequency for the PLL between 8MHz and 16MHz.
It doesn't mean that it won't actually work because out-of-specifiation things may still operate but without guarantie.
If the PLL does work your will have a core speed of 60MHz.
This is however not suitable for USB because it is not possible to derive the required 48MHz USB clock from it (the USB clock can be derived from the core clock using a fractional divider (/1, /1.5, /2.0, /2.5, /3.0 etc. which allows 60MHz, 40MHz, 30MHz, 24MHz etc.) but not 48MHz.
If you use
#define CLOCK_DIV 1
it will keep the input in range and give 120MHz core clock (which can still be divided down for the CPU if needed), but more importantly it allows the USB clock to be derived by using /2.5 (120MHz/2.5 = 48MHz).
Depending on the project version that you use I would expect that the build would have errored with the present setting since it checks that the PLL input is within range.
#if ((_EXTERNAL_CLOCK/CLOCK_DIV) < 8000000) || ((_EXTERNAL_CLOCK/CLOCK_DIV) > 16000000)
#error PLL input frequency must be between 8MHz and 16MHz
#endif
Also, when I ran your setup in the simulator, the USB driver exceptioned because it couldn't set the correct USB clock speed.
In any case this should fix it.
Regards
Mark
P.S. In the present developer's version there is in fact a target for a board with your chip and crystal - see K20FX512_120
The other thing that can go wrong with USB on custom boards is when the VREGIN in not connected to either 3.3V or 5V (this is used to generate the USB transceiver's voltage) and/or the VOUT33 pin doesn't have a suitable capacitor on it; 2.2uF low ESR is required otherwise it won't be stable enough for operation.