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91
NXPTM M522XX, KINETIS and i.MX RT / Re: Kinetis K60 Ethernet phy MDIO comm. problem
« Last post by mark on May 31, 2023, 08:01:57 PM »
Hi Ray

don't forget that the PHY has an address that is set via straps. Make sure that its address matches PHY_ADDRESS.
Or you can try SCAN_PHY_ADD which will scan all possible addresses to see whether the ID can be read on one of them.

Good luck

Regards

Mark

92
NXPTM M522XX, KINETIS and i.MX RT / Re: Kinetis K60 Ethernet phy MDIO comm. problem
« Last post by Ray on May 31, 2023, 03:05:07 AM »
Thanks Mark

It's strange how intellisense is spotty in my VS2022 for this file - but if I double click the kinetis_ENET.h in kinetis.c  the kinetis_ENET.h see's preprocessor info highlighted again.

Unfortunately, I'm still not getting anything but 0xffff when I query the phy registers on the command line. I know my MDIO lines are placed properly this time with a 1.5k p/u I think I need to very carefully attach some skywires to my previous MQX based design to see if MDIO is actually working on MQX code.

 
93
NXPTM M522XX, KINETIS and i.MX RT / Re: Kinetis K60 Ethernet phy MDIO comm. problem
« Last post by mark on May 30, 2023, 10:25:20 PM »
Hi Ray

In kinetis.c

#if (defined ETH_INTERFACE && defined ETHERNET_AVAILABLE && !defined NO_INTERNAL_ETHERNET)
/* =================================================================== */
/*                          Ethernet Controller                        */
/* =================================================================== */
    #include "kinetis_ENET.h"                                            // include Ethernet controller hardware driver code
#endif

It is not possible to include it from a header file since it contains code and then the code would be included in multiple locations.

VS normally handles highlighting well. Try a clean/rebuild which may sort it out.

Regards

Mark
94
NXPTM M522XX, KINETIS and i.MX RT / Kinetis K60 Ethernet phy MDIO comm. problem
« Last post by Ray on May 30, 2023, 08:08:57 PM »
Hi Mark,
As you know I have had moderate success interfacing a DP83848 phy into a uTasker ethernet based application despite the MDIO being inoperative.
As I debug this in the simulator, I can see when kinetis_ENET.h is called to initialize code, but I actually can't find where #include "../../Hardware/Kinetis/kinetis_ENET.h"  is added, so no preprocessor appear to be invoked from the settings in app_hw_kinetis.h, and all variables are flagged as error by the MSVC intellicode. 

If I add like this in the app_hw_kinetis.h
#include "../../Hardware/Kinetis/kinetis.h"                              // include the Kinetis processor header at this location
#include "../../Hardware/Kinetis/kinetis_ENET.h"                       // include the Kinetis processor header at this location

My preprocessor defines correctly highlight with intellicode, but I get hundreds of compiler errors.

Can you tell me where the kinetis_ENET.h is supposed to be #included?

Thanks
Ray

95
µTasker general / Re: How to identify code that causes a SW watchdog reset
« Last post by mark on April 29, 2023, 01:45:48 PM »
Hi

If you have code that may take a long time and causes a SW WDOG timeout (but not due to an error, as such) you can increase the watchdog value in (for example the i.MX RT project)

#define ACTIVATE_WATCHDOG()     UNLOCK_WDOG3(); WDOG3_TOVAL = (2 * 32000); WDOG3_WIN = 0; WDOG3_CS = (WDOG_CS_CLK_LPO | WDOG_CS_FLG | WDOG_CS_CMD32EN | WDOG_CS_EN); // enable watchdog with 2s timeout (32kHz reference)

or add re-triggers in the code [fnRetriggerWatchdog()].

To identify the location you can add a HW timer (single-shot that can be re-triggered) configured to a slightly lower timeout than the watchdog timeout.
Add a re-trigger of it to the macro
Code: [Select]
TOGGLE_WATCHDOG_LED()
and set a break point in its interrupt handler.

If this interrupt fires you can look to see which code is executing (step out of the interrupt or look at the call stack).

Regards

Mark
96
µTasker general / How to identify code that causes a SW watchdog reset
« Last post by FAQ on April 29, 2023, 01:43:19 PM »
If I have a project that sometimes causes a SW watchdog reset - but not due to a fault such as a hard fault - how can I catch the cause if the watchdog time itself doesn't support an interrupt?
97
NXPTM M522XX, KINETIS and i.MX RT / Re: i.MX RT Linker Script files for compatibility with MCUXpresso V11.5 and above
« Last post by mark on April 24, 2023, 09:36:28 AM »
Hi Ray

I don't think there is anything in the newer GCC versions that are greatly beneficial and older ones work fine:
Maybe there are some better warning messages in newer ones (pointing out potential code issues) but these are not critical.

Regards

Mark
98
NXPTM M522XX, KINETIS and i.MX RT / Re: i.MX RT Linker Script files for compatibility with MCUXpresso V11.5 and above
« Last post by Ray on April 24, 2023, 03:41:23 AM »
I'm using Visual Studio, but have a  complete c:\gnu\ folder where I keep all my gcc stuff together.  Currently running 9-2019-q4-major-win32.  Does this MCUXpresso update use a later gcc tool chain?  I see from the source (https://developer.arm.com/downloads/-/gnu-rm)   I see a 10-2020-q4-major-win32, and the current 10.3-2021.10-win32.   Is there a prefered tool chain that is best for iMX_RT's  and Kinetis  with uTasker?   
Ray
99
NXPTM M522XX, KINETIS and i.MX RT / i.MX RT Linker Script files for compatibility with MCUXpresso V11.5 and above
« Last post by mark on April 19, 2023, 01:32:37 PM »
Hi All

With the release of NXP's MCUXpresso V11.5, which is supplied with a newer version of the GCC tool chain, i.MX RT projects could no longer be build due to an incompatibility in the linker scripts.
Interestingly this however didn't affect Kinetis projects, where the same incompatibility was not experienced.

Originally attempts were made to identify what had changed and work around it but this proved to be a dead-end and so finally a new linker script was generated using the NXP SDK and then adapted to suit the uTasker code (such as inserting the same variable section references so that the initialisation code didn't need to be modified).

The result is that by swapping out original linker scripts against newer ones projects can be built with MCUXpresso versions pre-V11.5 and post.

At this time there are still some linker scripts to be adapted and tested but for the main usage I have attached the ones that can already be used (later they will be checked into the repository for general use)

- iMX_RT_10XX_FlexSPI_NOR.ld   This can be saved to \Applications\uTaskerBoot\GNU_iMX (overwriting the original) and allows the primary loader to be built for i.MX RT 10xx parts (excluding the i.MX RT 1064)

- iMX_RT_1064_FlexSPI_NOR.ld. This can be saved to \Applications\uTaskerBoot\GNU_iMX (overwriting the original) and allows the primary loader to be built for  the i.MX RT 1064

- iMX_RT_10XX_FlexSPI_NOR_BOOT.ld. This can be saved to \Applications\uTaskerSerialBoot\GNU_iMX (overwriting the original) and also to \Applications\uTaskerV1.4\GNU_iMX and allows the secondary loaders and application to be built for i.MX RT 10xx parts operating in RAM (the main operation configuration and always used by the serial loaders).

- iMX_RT_10XX_SDP_Boot.ld. This can be saved to \Applications\uTaskerSerialBoot\GNU_iMX (overwriting the original) and allows serial download protocol images for i.MX RT 10xx parts. This tends to be built in parallel with the serial loader and so, even if the SDP outputs are never used, it will stop the build failing.

Regards

Mark
100
NXPTM M522XX, KINETIS and i.MX RT / Re: i.MX RT 1062 Stock available to uTasker users
« Last post by mark on March 11, 2023, 10:41:32 PM »
Hi

The 0.65mm pitch part is designed/intended for 4 layer boards and the NXP EVKs are 4-layer designs allowing all pins to be used and also (according to them) passes FCC tests.

The only drawback is that some room around the device is needed for fan-out of the signal lines when many are used and when some GPIOs are not needed that means that it can be packed tighter together. See the attached screen shot of the chip on the NXP layout.  6-layer board would probably alleviate this.

NXP also has a detailed design guide at https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1050-crossover-mcu-with-arm-cortex-m7-core:i.MX-RT1050 "i.MX RT Hardware Development Guide for the MIMXRT1050/MIMXRT1060 Processor" - requires a log-in.

It is undeniable that more board layers and working with finer pitches and smaller holes will increase the price of a PCB and it is up to the designer to decide on such tradeoffs. However, in comparison to a K66, which - if it can be found and purchased at its normal price - tends to be much more expensive than an i.MX RT 10xx - maybe in the order of $10..15 and, coupled with much more peripherals and performance even paying more for a PCB should result in a cheaper (and potentially) better product.

I have also attached a screen shot of one of my designs where I use 77 ports/GPIO plus 1 x USB.

Regards

Mark

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