Author Topic: USB CDC initialization on Kinetis K66  (Read 293 times)

Offline AlexS

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USB CDC initialization on Kinetis K66
« on: April 06, 2020, 11:02:14 AM »
Hi,

So we've been running uTasker and USB successfully on our product for quite a while now. Unfortunately, we've had a few USB-related failures where the customer would plug the cable in his laptop and the MCU would just die and take D6 out as well.  Now, as you can probably see, we have an odd setup, there the 5V derived from our main 12V supply is fed into the USB5V line coming from USB through a diode and then going into VREGIN pins and powering the USB transceiver.

The reason we had to do this was to have the USB transceiver powered in order to initialize it at power-up, but I think we've done it wrong. Is there any way in which we can remove D6 and essentially only have VREGIN powered when the USB is plugged in? Detecting the "USB plugged" event and only initializing USB then.

Thanks!
Alex

Offline mark

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Re: USB CDC initialization on Kinetis K66
« Reply #1 on: April 06, 2020, 03:43:43 PM »
Hi Alex

The VREG is used for the USB transceiver (as you know) ad can also be used to supply 3V3 to other parts of the circuit, or eve the processor itself in a USB power supplied circuit.

If only used for the USB transceiver the VREGIN can be connected to the USB host's 5V line so that it is supplied only when the USB is connected - it doesn't need to be detected and initialised only when connected since USB can otherwise initialised earlier
- this is certainly the case for FS USB device
- in case you use the HS device on the K66 the PHY's PLL will possibly not lock when the supply is not connected, this stopping the initialision from working

In the second case it may indeed be necessary to monitor the power supply to ensure that it can start.
Another option may be to detect that the PLL can't lock and abort initialisation, afterwards using the PLL lock interrupt (assuming one exists) as detection indication and allowing the initialision to continue/repeat.

I don't understand the HW issue of leaving VREG supplied all the time since this is also what some of the reference designs do but if it needs to be avoided I believe the the PLL control is what is needed to control the operation, but I haven't actually a method to manage this at the moment.

Regards

Mark