Author Topic: mcf52233 clock off by 20% with CW10 (sometimes)  (Read 3449 times)

Offline alager

  • Jr. Member
  • **
  • Posts: 92
    • View Profile
mcf52233 clock off by 20% with CW10 (sometimes)
« on: July 18, 2014, 11:47:59 PM »
We have a mature product that was developed on CW7.  We've ported it over to CW10.4, and have found that some boards, identical in measured 25Mhz xtal input, are running about 20% slower.  40Mhz instead of 50Mhz.
This is causing the uart baud rate calculations to be wrong among other things.
Below is the pll initialization function.  I've checked the LOCK bit in SYNSR and it indicates that the PLL is locked.
 
Code: [Select]
void pll_init(void)
{
  MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 25MHz / 5 = 5MHz
 
  /* The PLL pre-divider affects this!!!
  * Multiply 25Mhz reference crystal /CCHR by 10 to acheive system clock of 50Mhz --> MCF_CLOCK_SYNCR_MFD(3)
  */
 
  MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;
 
  while (!(MCF_CLOCK_SYNSR & MCF_CLOCK_SYNSR_LOCK))
  {
  }
}

 
I've tried erasing the chip completely and then re-programming to no avail.  If I load up one of the S19 files that was generated with CW7, then there are no issues with any of the boards.
 
chip markings are different only in the third line:
good: qaaq932
bad: qea1042

Any ideas on how to correct this would be greatly appreciated!
Aaron
« Last Edit: July 18, 2014, 11:58:57 PM by alager »

Online mark

  • Global Moderator
  • Hero Member
  • *****
  • Posts: 3068
    • View Profile
    • uTasker
Re: mcf52233 clock off by 20% with CW10 (sometimes)
« Reply #1 on: July 18, 2014, 11:57:58 PM »
Hi Aaron

I think that it would be best to compare the assembler code in the two cases because there must be a difference.
I notice that the PLL code is not from the uTasker project but is otherwise effectively the same.

Is MCF_CLOCK_SYNSR declared as a volatile location so that the PLL is really locked when the code continues(?).

Regards

Mark




Offline alager

  • Jr. Member
  • **
  • Posts: 92
    • View Profile
Re: mcf52233 clock off by 20% with CW10 (sometimes)
« Reply #2 on: July 19, 2014, 12:15:27 AM »
Mark,

Yes, you are right, we are using the standard start up files generated by freescale.  Porting our uTasker project over to CW10 was a bit of  a hassle, so we opted to use the standard files.

SYNSR is a volatile:
#define MCF_CLOCK_SYNSR                      (*(vuint8 *)(0x40120002))

Single stepping through the init function while watching the clockout pin, I can see the frequency at 25Mhz, then when SYNCR is set, clockout goes to 40Mhz, and stays there, like it's stable.

Are you aware of any trim values, or anything like that on this chip?

Thanks,
Aaron

Online mark

  • Global Moderator
  • Hero Member
  • *****
  • Posts: 3068
    • View Profile
    • uTasker
Re: mcf52233 clock off by 20% with CW10 (sometimes)
« Reply #3 on: July 19, 2014, 04:24:40 PM »
Aaron

The latest uTasker releases contain CW10.x projects configurations.

However I looked at your code more closely and may be able to explain the problem:

MCF_CLOCK_CCHR =0x05; // The PLL pre divider - 25MHz / 5 = 5MHz
This divides the input clock by 6 and not 5.

Note the uTasker code:
MCF_CLOCK_CCHR  = (PRE_DIVIDER - 1);

Therefore I think that your input clock to the PLL is 4.1666MHz and not 5MHz.


The PLL is set with
MCF_CLOCK_SYNCR = MCF_CLOCK_SYNCR_MFD(3) | MCF_CLOCK_SYNCR_CLKSRC| MCF_CLOCK_SYNCR_PLLMODE | MCF_CLOCK_SYNCR_PLLEN ;

Comparing with the uTasker code
MCF_CLOCK_SYNCR = ((((PLL_MUL - 4)/2) << 12) | CLKSRC | PLLMODE | PLLEN | (POST_DIVIDE << 8 ));

I think that the post divider is 1 and the multiplier is 10, which would give a PLL output frequency of 41.6666MHz




In the uTasker configuration the input divider value is declared using:
        #define PRE_DIVIDER                    5                         // warning: in first silicon this can not be changed!

Note the warning about the silicon issue. Early devices would set the divide to 5 by default and not allow it to change - this was an errate that I reported to Freescale a long time ago (2006 - see https://community.freescale.com/message/13535#13535) and was eventially added it to the chip errata in (about) the rev. 5 version in about 2009.

This suggests that you have some chips with the errata and some without. The ones with the errate "mask" the setting error and the 'good' chips show it.

Regards

Mark

« Last Edit: July 19, 2014, 04:36:27 PM by mark »

Offline alager

  • Jr. Member
  • **
  • Posts: 92
    • View Profile
Re: mcf52233 clock off by 20% with CW10 (sometimes)
« Reply #4 on: July 21, 2014, 05:12:59 PM »
Mark,

Thanks for the analysis!  I did miss the part (PRE_DIVIDER - 1).  Those HW engineers can make some wily register values at times.  :o

Aaron