Teensy 4.1 with Ethernet Kit

[mark]

Hi All

Guess what I received for Christmas?

A Teensy 4.1 with Ethernet Kit !!!

So I soldered the Ethernet Kit together and built the uTasker Loader and an application with Ethernet features as found here: https://www.utasker.com/iMX/Teensy_4_1.html

I did have to adapt the PHY configuration slightly to ensure it was configured to match the HW's clocking but then it started working as it should.

Regards

Mark

[cebrax]

Hello Mark,

What would be the modifications for the PHY to work?

I have run the 1.4.12, however MDIO line is always high, although there is some clocking at 2.5MHz at power-up. Also, when I try to "Dump PHY registers", the iMX restarts and last reset cause shows "???" but I think it was a watchdog reset.

[mark]

Hi

I had the same effect when I first tried but I haven't checked in modifications yet.

These are however the changes I have against the checked in version as of today.

1. app_hw_iMX.h

#elif defined TEENSY_4_1
    #define MII_MANAGEMENT_CLOCK_SPEED    2500000                        // typ. 2.5MHz Speed
  //#define MSCR_HOLDTIME          7
    #define _DP83825I
    #define ETHERNET_RMII                                                // RMII mode of operation instead of MII
    #define RESET_PHY                  PIN_GPIO_B0_14_GPIO2_IO14         // control the PHY's reset so that its configuration can be controlled
    #define PHY_STRAP_A0               PIN_GPIO_B1_04_GPIO2_IO20
    #define PHY_STRAP_RMII_SLAVE       PIN_GPIO_B1_05_GPIO2_IO21
    #define PHY_STRAP_A1               PIN_GPIO_B1_06_GPIO2_IO22

    #define ASSERT_PHY_RST()           _CONFIG_DRIVE_PORT_OUTPUT_VALUE(2, (RESET_PHY), (0), (PORT_SRE_SLOW | PORT_DSE_MID)) // start with PHY reset asserted and INTPR/NAND_TREE forced high
    #define CONFIG_PHY_STRAPS()        _CONFIG_DRIVE_PORT_OUTPUT_VALUE(2, (PHY_STRAP_A0 | PHY_STRAP_A1 | PHY_STRAP_RMII_SLAVE), (PHY_STRAP_A0 | PHY_STRAP_RMII_SLAVE), (PORT_SRE_SLOW | PORT_DSE_MID))
    #define FNFORCE_PHY_CONFIG()       _SETBITS(2, RESET_PHY); fnDelayLoop(5000) // take PHY out of reset and wait 5ms so that it will be ready for following operations
    #define FORCE_PHY_CONFIG
    #define PHY_ADDRESS                0x01                              // address of external PHY on board (fixed address used when scan not enabled)
    #define PHY_IDENTIFIER             0x2000a140                        // National/TI DP83825I identifier

    #define PHY_INTERRUPT              PIN_GPIO_B0_15_GPIO2_IO15
    #define PHY_INTERRUPT_PORT         PORT2
    #define MDIO_ON_PORT2
    #define INTERRUPT_TASK_PHY         TASK_NETWORK_INDICATOR            // enable link state output messages

Note that in order to ensure the PHY starts as slave (and not master) the PHY_STRAP_RMII_SLAVE is added.

2. MDIO_ON_PORT2 controls the MDIO pin-out but in kinetis_ENET.h this setup needs to be corrected as follows:

        #elif defined MDIO_ON_PORT2
        _CONFIG_PERIPHERAL_LOOPBACK(GPIO_B1_14, ENET_MDC, (PORT_DSE_MID)); // ENET0_MDC on GPIO2-30 (alt. function 0)
        IOMUXC_ENET_MDIO_SELECT_INPUT = IOMUXC_ENET_MDIO_SELECT_INPUT_GPIO_B1_15_ALT0;
        _CONFIG_PERIPHERAL(GPIO_B1_15, ENET_MDIO, (PORT_PS_UP_ENABLE | PORT_DSE_MID | PORT_SRE_FAST | PORT_SPEED_MID)); // ENET0_MDIO on GPIO2-31 (alt. function 0) with pullup enabled

since the MDIO line was not set correctly for driving its output (it is bi-directional).

I believe these where the only changes needed for it to then operate., although I don't think that the state change interrupt is presently working (less important for basic operation). This is probably due to the need to set up the PHY interrupt registers a little differently.

Regards

Mark

[cebrax]

Thanks for this, Mark! It started sending out the data..

However, it seems like I have fried my PHY chip, as I cannot see any voltage on RBIAS Pin(Pin 14)..

[mark]

Hi

Pin 14 to ground has a 6.49k resistor so the resistance from pin 14 to GND measures about this.
I then have 1.5V on the pin when it is operating.

Do you know how yours may have failed?

Regards

Mark

[cebrax]

Hey Mark,

Yes, when unpowered, I measure that resistance of 6.49k ohms.
However, when operating, there is 0V on this pin. Although I see 50MHz coming to the chip, I don't see anything on Pin 12, but that could be normal as it is operating in RMII Slave Mode..

I guess I have screwed it by incorrectly connecting the magjack, maybe by floating the center taps by not connecting to GND via a 100nF cap, or maybe connecting them in reverse, or maybe shorting some pins of the PHY when trying to measure them by the scope probe..

I have ordered a new chip and will try and notify of the results. But I think it will not be early due to new year..

Thank you for your help

[mark]

Hi

I understand that the magjack can be connected 180° reversed and the Ethernet connection still works (but the LED doesn't).

Since I also measured some signals I know that it is a bit delicate as it is small and there is not a lot of room and I was also worried about shorting pins in the process.
In any case I am sorry to hear that yours could be dead for whatever reason - it is frustrating when something like that happens and a new one needs to be waited for.

Regards

Mark